3) Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16- byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown below: Tag 4 bits Block 2 bits Offset 2 bits The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50, 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. Fill out the following tables: a) Address Hit Reference or Miss Comments b) Show the final contents of cache for direct addressing: Block Cache Contents Tag (represented by address)
3) Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16- byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown below: Tag 4 bits Block 2 bits Offset 2 bits The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50, 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. Fill out the following tables: a) Address Hit Reference or Miss Comments b) Show the final contents of cache for direct addressing: Block Cache Contents Tag (represented by address)
Chapter11: Operating Systems
Section: Chapter Questions
Problem 21VE
Related questions
Question
![3) Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-
byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout
the course of running a program. Suppose this computer uses direct-mapped cache. The format of a
memory address as seen by the cache is shown below:
Tag
4 bits
Block
2 bits
Offset
2 bits
The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50,
0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. Fill out the following tables:
a)
Address
Hit
Reference or
Miss
Comments
b) Show the final contents of cache for direct addressing:
Block
Cache Contents
Tag
(represented by address)](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Faacafc71-04a2-4ee1-98a1-244fbc38e4f1%2Fcc4a0a37-d6c6-432e-8e5b-36f9dcd52caa%2Fxsocuh9_processed.png&w=3840&q=75)
Transcribed Image Text:3) Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-
byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout
the course of running a program. Suppose this computer uses direct-mapped cache. The format of a
memory address as seen by the cache is shown below:
Tag
4 bits
Block
2 bits
Offset
2 bits
The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50,
0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. Fill out the following tables:
a)
Address
Hit
Reference or
Miss
Comments
b) Show the final contents of cache for direct addressing:
Block
Cache Contents
Tag
(represented by address)
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