T8

Hardware & Architecture HW #5 - 100 Pts 6. a. (8 Pts) Label the Boolean output of each gate. Note: The labels you need are giving in the Table for Part b; you only need to map each to the correct location in the circuit. b. Using the table provided, derive a Truth Table for the Output B Inputs (3 Pts) D 3 Pts 2 Pts 3 Pts 3 Pts 2 Pts 3 Pts. A B C D A A+B T BC 3 Pts C+D A+ B+ BC (A + B)(C + D) 0 0 0 0 00 0 1 0 0 1 0 0 0 1 1 O 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 00 0 1 0 0 1 1 0 1 0 0 1 1 1 1 00 1 0 1 1 1 1 0 1 1 1 3 Pts A+B+BC+(A + B) (C + D)

Plz solve this DLD

Question 3: A combinational circuit is specified by the following three Boolean functions: F1(A, B , C) = Σ(1, 4, 6) F2(A, B, C) = E(3, 5) F3(A, В, C) 3D 2(2, 4, 6, 7) Implement the circuit with a 3x8 decoder and NAND gates only (2-input and 3-input NAND gates are allowed)

3- Use NAND gate, NOR gate, or combinations of both to implement the following expression:- a) X=A [B+C (D +E)] b) X = B (CDE + EF G) (A B + C)

4- The data sheet of a quad two-input NAND gate specifies the following parameters: IoH (max.)=0.4 mA, VOH (min.) =2.7 V, VIH (min.) =2V, VIL (max.)=0.8 V, VOL (max.)=0.4 V, IOL (max.)=8 mA, IL (max.)=0.4 mA, IH (max.)=20µA, ICCH (max.)=1.6 mA, ICCL (max.)=4.4 mA, tpLH =tpHL=15 ns and a supply voltage range of 5 V. Determine (a) The average power dissipation of a single NAND gate, (b) The maximum average propagation delay of a single gate, (c) The HIGH-state noise margin and (d) the LOW-state noise margin

Question 5: F(a,b,c,d)=I(0,1,3,6,10,11,14) Implement the above boolean function using a. 4:1 MUX(s) and 2:1 MUX(s) [both in the same circuit]. b. 8:1 MUX You can also use minimal number of BASIC gate(s) with the above-mentioned decoders.

F(A, B, C, D) = Em(0, 1, 2, 6, 9, 10, 11, 13, 15), implement the following function F by using one 4-to-1 multiplexer and external gates (OR, AND, NOT...).

Implement the following function using NAND gate only: a) F (D,C,B,A) =E (4,5,7,12,14,15), d (3,8,10) b) Y (A,B,C,D) = [ (0,2,3,7), d (4,5) %3D

Logic design & Circuits

You have to design a logic diagram which can implement the complement of following by using NAND gates ONLY. F (A, B, C, D) = Σ (0, 1, 2, 3, 6, 10, 11, 14)

Simplify the following expression and implement it using NOR gate. F(A,B,CD)-Em(1,2,4,11,13,14,15)+Ed(0,5,7,8,10)

503220-3 Digital Logic Design Homework #1 Spring 2022 DUE: Sunday 27/2/2022 1. Consider a Boolean Algebra (1) a) Show that i. X.y + x'.z+ yz = x.y+x'.z ii. (a + b)'(a' + b)' = 0 2. Given implement it with AND, OR and inverter gates. (2) 3. Find the complement of the following expression: (1) 4. Algebraically simply the following expressions: (2) F = abc + a'bc + a'b'c +abc' + a'b'c' b. F = y(wz'+ wz) + xy a.

->Simplify the Boolean function and design its logic gates(NAND and NOR). F1(x,y,z) = xy’z+xyz+y’z’ NOTE: Using NAND and NOR GATES & Handwritten form (NEAT).

its my digital system class.

Q5-A Explain how the OR logic gate can be represented by using NAND logic gate 1 Add file Q5-B Simplify following expression by using K-Map X = BC D + ĀBCD+ AB C D + Ā BCD + A BCD + Ā BC D + ĀBC D + АВС D + АВС D 1 Add file

Implement the diagram in part b and verify its function experimentally by constructing a truth table from the test data.

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