COE 608 UoIT Quizzes and Midterm

.pdf

School

York University *

*We aren’t endorsed by this school

Course

3650

Subject

Computer Science

Date

Apr 3, 2024

Type

pdf

Pages

Uploaded by ProfessorMonkeyPerson2705

1 UOIT: Electrical, Computer, and Software Eng. Computer Architecture- ELEE3140 Fall 2015 Quiz 1 Date: 23/09/2015 Q1: The main units in a computer system are: a) CPU, Memory, I/O devices, and Interconnection network. b) ALU, Control Unit, RAM and Hard disk. c) CPU, ALU, MMU, and Data Bus. d) Data Bus, Address Bus, Control Bus, and CPU. Q2: The RAM is: a) Volatile memory. b) Non-Volatile memory. c) It is of unlimited size. d) All of the above. Q3: The RAM is called Random access memory because: a) It works in a random fashion. b) Any location in the RAM can be accessed in a short and fixed time. c) The data is stored randomly. d) The data is retrieved randomly. Q4: The following are listed based on the access speed: a) Registers, Cache, RAM and then Hard disk. b) Hard disk, RAM, Cache, and then registers. c) Cache, Registers, RAM, and then Hard disk. d) Cache, RAM, Hard disk, and then registers. Q5: The program counter (PC) always carries: a) The address of the instruction being executed. b) The instruction being executed. c) The address of the instruction to be executed next. d) The Instruction to be executed next. This study source was downloaded by 100000804524329 from CourseHero.com on 02-14-2024 19:55:28 GMT -06:00 https://www.coursehero.com/file/27852669/Quiz-1-ELEE3140-F15pdf/

2 Q6: The instruction register (IR) always carries: a) The address of the instruction being executed. b) The instruction being executed. c) The address of the instruction to be executed next. d) The Instruction to be executed next. Q7: The instruction: Load R2, LOC: a) Will load the contents of R2 into memory location addressed by LOC. b) Will load the contents of the memory location addressed by LOC into R2. c) Will load the characters ‘R’ and ‘2’ into memory location LOC. d) Will load the characters ‘L’, ‘O’,and ‘ C ’ into R2. Q8: The instruction: Store R2, LOC: a) Will store the contents of R2 into memory location addressed by LOC. b) Will store the contents of the memory location addressed by LOC into R2. c) Will store the characters ‘R’ and ‘2’ into memory location LOC. d) Will store the characters ‘L’, ‘O’,and ‘ C ’ into R2. Q9: In a 5-bit register implementation, the result of the operation (-2) + (-9) in binary is: a) 10101. b) 11011. c) 01011. d) 110101. Q10: In a 5-bit register implementation, the result of the operation (-13) + (-9) in binary is: a) 101010 . b) 01010 . c) 10110. d) 11111. This study source was downloaded by 100000804524329 from CourseHero.com on 02-14-2024 19:55:28 GMT -06:00 https://www.coursehero.com/file/27852669/Quiz-1-ELEE3140-F15pdf/ Powered by TCPDF (www.tcpdf.org)

1 UOIT: Electrical, Computer, and Software Eng. Computer Architecture- ELEE3140 Fall 2015 Quiz 3 Date: 07/10/2015 Q1: After executing this code, what are the contents of R2? Move R2, #NUMBERS Load R3, 8(R2) Store R3, (R2) ORIGIN 0x500 NUMBERS: DATAWORD 10, 20, 30 RESULT: RESERVE 4 Solution The contents of: R2=0x500 Q2: After executing this code, what are the contents of R3? Move R2, #NUMBERS Load R3, 4(R2) Add R3, R3, (R2) ORIGIN 0x500 NUMBERS: DATAWORD 10, 20, 30 RESULT: RESERVE 4 Solution The contents of: R3=30 Q3: After executing this code, what are the contents of R3? Move R2, #NUMBERS Load R3, 4(R2) Add R3, R3, R2 ORIGIN 0x500 NUMBERS: DATAWORD 10, 20, 30 RESULT: RESERVE 4 Solution The contents of: R3=0x514 This study source was downloaded by 100000804524329 from CourseHero.com on 02-14-2024 19:56:51 GMT -06:00 https://www.coursehero.com/file/27852545/Quiz-2-solution-ELEE3140-F15pdf/

2 Q4: After executing this code, what are the contents of R3? Move R2, #NUMBERS Load R3, 4(R2) Load R3, (R3, R2) ORIGIN 0x500 NUMBERS: DATAWORD 10, 8, 30 RESULT: RESERVE 4 Solution The contents of: R3=30 Q5: After executing this code, what are the contents of PC (Program Counter)? ORIGIN 0x100 Move R2, #NUMBERS Load R3, 4(R2) Load R3, (R3, R2) ORIGIN 0x500 NUMBERS: DATAWORD 10, 8, 30 RESULT: RESERVE 4 Solution The contents of: PC=0x10C Q6: After executing this code, what is the contents of memory location addresses by RESULT? ORIGIN 0x100 Move R2, #NUMBERS Load R3, 8(R2) Add R3, R3, #50 Store R3, 12(R2) ORIGIN 0x500 NUMBERS: DATAWORD 10, 8, 30 RESULT: RESERVE 4 Solution The contents of: (RESULT) =80 This study source was downloaded by 100000804524329 from CourseHero.com on 02-14-2024 19:56:51 GMT -06:00 https://www.coursehero.com/file/27852545/Quiz-2-solution-ELEE3140-F15pdf/ Powered by TCPDF (www.tcpdf.org)

1 UOIT: Electrical, Computer, and Software Eng. Computer Architecture- ELEE3140 Fall 2015 Quiz 3 Date: 21/10/2015 Q1: After executing this program, what are the contents of R2, R3, R4, R5, R6, and R7? Load R2, #A_VEC Load R3, #B_VEC Load R4, #3 And R5, R5, R0 LOOP: Load R6, (R2) Load R7, (R3) Multiply R6, R6, R7 Add R5, R5, R6 Add R2, R2, #4 Add R3, R3, #4 Subtract R4, #1 Branch>0 LOOP Load R7, # RESULT Store R5. (R7) End ORIGIN 500 A_VEC: DATAWORD 05, -20, 10 B_VEC: DATAWORD 09, 04, 07 RESULT: RESERVE 4 Solution R2 R3 R4 R5 R6 R7 RESULT 500 512 3 0 05 09 35 504 516 2 35 -20 04 -80 508 520 1 -45 10 07 70 512 524 0 25 524 25 The contents of: R2=512, R3=524, R4=0, R5=25 R6=7 R7=524 This study source was downloaded by 100000804524329 from CourseHero.com on 02-14-2024 19:55:47 GMT -06:00 https://www.coursehero.com/file/27852584/Quiz-3-solution-ELEE3140-F15pdf/ Powered by TCPDF (www.tcpdf.org)

1 UOIT: Electrical, Computer, and Software Eng. Computer Architecture- ELEE3140 Fall 2014 Quiz 4 Date: 14/11/2014 Q1: How many chips you need to build a memory module of size 4M  8 bits, if you only have chips of size 256K  1 bits. a) 128 b) 96 c) 4096 d) 1024 Q2: A block-direct-associative cache consists of a total of 64 blocks. The main memory contains 1K blocks, each consisting of 8 words. Each word is 4 bytes. Assuming a 16-bit byte-addressable address space, how many bits are there in each of the Tag, Set, and Word fields? a) Tag= 5 bits. Block=6 bits, Word= 5 bits. b) Tag= 6 bits. Block=5 bits, Word= 5 bits. c) Tag= 5 bits. Block=5 bits, Word= 5 bits. d) Tag= 5 bits. Block=4 bits, Word= 5 bits. Q3: The memory access time is: a) The time from initiation to completion of a word or byte transfer. b) The minimum time delay between initiations of successive transfers. c) The time required to read a word from the register file. d) The time needed to execute one BRANCH instruction. Q4: Compared to the static RAM, the dynamic RAM is: a) Slower, Cheaper, Simpler, and always needs refreshing. b) Slower, Expensive, Complex, and always needs refreshing. c) Slower, Cheaper, Simpler, and does not need refreshing. d) Faster, Cheaper, Simpler, and always needs refreshing. Q5: The Double-Data-Rate (DDR) SDRAM: a) Transfers data on the rising and falling edges of its own clock cycle. b) Transfers data only on the rising edge of its own clock cycle. c) Transfers data only on the falling edge of its own clock cycle. d) Transfers data on the rising and falling edges of the processor’s clock cycle. Q6: The hierarchy of the memory in a computer is (starting from the processor): a) Registers, Cache, RAM, and Hard disk. b) Registers, RAM, Cache, and Hard disk. c) RAM, Registers, Cache, and Hard disk. d) Cache, RAM, Registers, and Hard disk. Q7: The flash memory is made of: a) EEPROM cells. b) Dynamic RAM cells. c) Read Only Memory cells. d) Static RAM cells. This study source was downloaded by 100000804524329 from CourseHero.com on 02-14-2024 19:57:15 GMT -06:00 https://www.coursehero.com/file/27852567/Quiz-4-solution-ELEE3140pdf/ Powered by TCPDF (www.tcpdf.org)

Your preview ends here

Eager to read complete document? Join bartleby learn and gain access to the full version