T11

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School

Swinburne University of Technology *

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Course

EEE20001

Subject

Electrical Engineering

Date

Oct 30, 2023

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pdf

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2

Uploaded by bercianoj

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Digital Electronics - Tutorial 45 of 46 Tutorial 11 Solution Q1 Present Next Present State State Output X=0 1 X=0 1 a a b 1 0 b b h 0 0 c h a 1 1 d g h 0 0 e e b 1 0 f h a 1 1 g d h 0 0 h b c 1 0 b=g h=h e=e b=g h=h a=e b=d h=h d=g h=h e=g f=g e=g b=f a b c d e f g b c d e f g h a=e, b=d, b=g, c=f, d=g a=e, b=d=g, c=f Q2 & Q3 a b c h 0/1 1/0 0/0 1/0 0/1 1/1 1/0 0/1 c Y=1 X? 0 1 Y=1 X? 0 1 X? X? 0 1 0 1 Y=1 a b h state X/Y Legend Default Y=0
Digital Electronics - Tutorial 46 of 46 Q4) -------------------------------------------------------- -- State Machine implementation for Tutorial 10 Q 4) -------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164. ALL ; entity SMExample is Port ( reset : in std_logic ; clock : in std_logic ; X : in std_logic ; Y : out std_logic ); end entity SMExample; architecture Behavioral of SMExample is type StateType is (a, b, c, h); signal state, nextState : StateType; begin sync: process (reset, clock) begin if (reset = '1') then state <= a; elsif ( rising_edge (clock)) then state <= nextState; end if ; end process sync; comb: process (X, state) begin nextState <= a; Y <= '0'; -- set default output case (state) is when a => if (X='1') then nextState <= b; else nextState <= a; Y <= '1'; end if ; when b => if (X='1') then nextState <= h; else nextState <= b; end if ; when c => Y <= '1'; if (X='1') then nextState <= a; else nextState <= h; end if ; when h => if (X='1') then nextState <= c; else nextState <= b; Y <= '1'; end if ; end case ; end process comb; end architecture Behavioral;
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