physical_layer

Q.2) What is the method of arbitration of the PCI bus? Modify the following diagram arbitration, when there is a device C request use the PCI bus at the same time with device B. The arbiter services the device A then C to transfer 2 data for each, then service device B to transfer 1 data. CLK REOA REQ-S %3D GNTEA GNT-B %3D FRAME %3D %3D IRDY %3D TRDY Address Data Addre Data AD

solve part (iv), let the writing easy to read pls.. thanks

Q3. b) Suppose you want to transmit the 10-bit message [101101101] by Pulse code Modulation (PCM). Using clearly labeled diagrams, show the encoding the bit sequence using the following PCM waveform types: i) Bipolar RZ Signal ii) RZ-AMI iii) Bi – o - L iv) Delay modulation

Write TRUE if the statement is correct but if it’s false, change the underlined word or groupof words to make the whole statement correct. The subject is basic electronics. please answer my questions. thanks

Q4. Consider the 16-QAM digital modulation scheme (a) What does the abbreviation QAM stand for? (b) Sketch an I-Q constellation diagram for this modulation scheme. (c) State the number of bits per symbol. (d) If the bit rate that is achieved with this modulation scheme is 256 Mbit s, what is the baud (symbol) rate?

Draw a block diagram of a typical digital communications system (both transmit and receive paths) and briefly describe what happens within the Source Encoder and Channel Encoder elements, making sure to mention the nature of the signal generated by these blocks. b)

What digital component is implemented in the following VHDL code? What is the role of Process statement in this VHDL code? Explain in detail.   LIBRARY ieee; USE ieee.std_logic_1164.all;   ENTITY test3 IS    PORT (D, Clock : IN STD_LOGIC ;      Q : OUT STD_LOGIC ) ; END test3 ;   ARCHITECTURE Behavior OF test3 IS       BEGIN      PROCESS    BEGIN       WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ;    END PROCESS ;   END Behavior ;   G. Complete the following VHDL code to implement a 2-to-4 binary decoder with an enable input.   LIBRARY ieee ; USE ieee.std_logic_1164.all ;   ENTITY dec2to4 IS PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ;   ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT     END Behavior ;

Question 5: a) In the context of WCDMA, answer the following questions: What is the chip rate of WCDMA? i. ii. What is the duration for WCDMA frame? iii. For the figure shown below, what is the spreading factor? Symbol iv. V. vi. vii. Data Spreading code Spread signal Datax code Spreading What is the corresponding processing gain? For the figure shown below, what is the multiplexing mode used? Uplink Downlink Frequency Time WCDMA has a frequency reuse of 1 between different cells. What does that mean? If fast fading occurs when the path difference between two received signals is half wavelength. Calculate the path difference at a frequency equals to 2 GHz.

(b) In a junction of road instaled with traffic light, the sensor circuit with capabilties to detect a vehicle is planned to be buikl. By using the a.c bridge, discuss types of ac bridge that can be used for that purpose. Explain the concept using bock diagram of how the circut is connected and used with microprocessor.

VLSI Wafer Yield  Given the defect density D= and chip area A, use Murphy's yield model to estimate the chip yield. Calculate for D=0.5 defects/cm2 D=0.5 defects/cm2 and A=1.5 cm2 A=1.5 cm2.

Let the writing easy to read please..

A digital signaling system is required to operate at 9600 bps. a. If a signal element encodes a 4-bit word, what is the minimum required band-width of the channel? b. Repeat part (a) for the case of 8-bit words.

In digital communication .explain all the methods/mechanism used for the minimization of bit error rate (BER) . Subject is Communication system.

Mathematically describe the differences between DSB-AM, USB-AM, and QAM demodulators at the receiver/demodulator side; then, interpret those differences of mathematical descriptions in detail based on the physical concept level understanding. If we have DSB-AM modulator and demodulator, launching the USB-AM scheme demands the change of demodula- tion structure at the receiver? What about the case of launching the QAM scheme; it requires change of demodulator structure at the receiver? If the USB-AM and/or QAM requires changes, mathematically describe the changes. If a user's receiver has only the demodulator for DSB-AM, explain how the transmitter with the QAM modulator can support that user. Describe as much as you can for the full credit.

The following text "Cannot discriminate among close optical channels" would be best describe: Select one: a. Optical fibers . WDM modulators c. Optical sources Od. Optical detectors

3.18 A PCM system uses a uniform quantizer followed by a 7-bit binary encoder. The bit rate of the system is equal to 50 x 10 bis. (a) What is the maximum message bandwidth for which the system operates satisfactorily? (b) Determine the output signal-to-(quantization) noise ratio when a full-load sinusoidal modulating wave of frequency 1 MHz is applied to the input. of entially en- 3.26 C

5. Which one of the following is used to minimize reflections present in a bus cable: (a) coupler panels (b) bus terminators (c) shielded twisted pair cables (d)fiber optics. 6.A bus that supports the transfer of data in both directions is referred to as: (a) universal (b) bidirectional (c) asynchronous (d) there is no need for data conversion. 7. Inverter and transformer rectifier units are sources (a)secondary power (b)primary power (c)emergency power (d)none Solve all

In a digital communication,explain all the methods/mechanism used or the minimization of Bit error rate (BER).Also state that which method/mechanism is preferred and why? subject is communication system.

+A logic 1 → Am logico H.W. for Bipolar -A -Atn Vth ?? Prove>

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Answer all questions below: 1. Draw the general block diagram of Frequency Division Multiplexing (FDM) 2. Multiplexing is a technique that allows the (simultaneous) transmission of multiple signals across a single data link. Figure Q2 below shows a multiplexer with four 500 kbps data stream inputs and 1 data stream output where the unit of data is 1 bit. Determine: i. ii. iii. 500 kbps The type of multiplexing technique used. The input bit duration. The output bit rate. 500 kbps 500 kbps. 500 kbps. ... ... ... 1 0 1 0 1 0 1 0 0000 1 1 1 1 0 1 0 0 MUX Figure Q2 Frames 0101 0001 110100010101

VHDL

Q1. a) For the circuit shown in Figure 1, answer the following questions: D1 Y D2 Figure 1 i. Explain the working of the circuit for different input combinations along with the truth-table. ii. Modify the circuit diagram of Figure 1 to work as a NAND gate circuit. iii. Explain the working of the NAND gate circuit for different input combinations along with the truth-table.