ECE526-HW#1 - Solution

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526

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Electrical Engineering

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Dec 6, 2023

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1. What are the reasons to avoid clocking a flipflop from a logic gate or from another flipflop? Have the design synchronous and more noise immune. Also, get rid of the ripple clock behavior for the circuit. (Lecture #1) 2. Write the header for a Verilog description of an eight-bit adder/subtractor, including carries/borrows. This does not include writing the functional code for the module but it does include all the I/O statements as well as a comment section at the top. module adder_sub(x, y, input_carry, sum, output_carry); input [7:0] x; input [7:0] y; input input_carry; output reg [7:0] sum; output reg output_carry; reg [8:0] c; 3. A 4-variable logic function that is equal to 1 of any three or all four its input variables are equal to 1 is called a majority function. a. Write a gate-level Verilog module with four inputs and one output that implements the majority function using the basic gate primitives and, or, xor, not . module majority_gl(f,x1,x2,x3,x4); input x1,x2,x3,x4; output f; wire w1,w2,w3,w4; and a1(w1,x1,x2,x4); and a2(w2,x2,x3,x4); and a3(w3,x1,x3,x4); and a4(w4,x1,x2,x3); or o1(f,w1,w2,w3,w4); endmodule b. Write a dataflow Verilog module with the same inputs and outputs that implements the same majority function using continuous assignment statements. module majority_df(f,x1,x2,x3,x4); output f; input x1,x2,x3,x4; assign f = ((x1 & x2 & x4) | (x2 & x3 & x4) | (x1 & x3 & x4) | (x1 & x2 & x3)); endmodule
4. Using structural Verilog and gate level operators, write a Verilog module to implement a two bit magnitude comparator. This comparator should have three active high outputs: one for equal, one for A > B and one for B > A. module comparator( input [ 1 : 0 ] A , B , output ALTB, EQ, AGTB // L=Less , G=Greater, E=Equa ); wire tmp1,tmp2,tmp3,tmp4,tmp5, tmp6, tmp7, tmp8, An0, An1, Bn0, Bn1; reg AGTB, ALTB, EQ; not not_A0(An0,A[0]); not not_A1(An1,A[1]); not not_B0(Bn0,B[0]); not not_B1(Bn1,B[1]); // A = B output xnor xnor1(tmp1, A [ 1 ], B [ 1 ]); xnor xnor2(tmp2, A [ 0 ], B [ 0 ]); and and3(EQ,tmp1,tmp2); // A less than B output and and1(tmp3,An0,An1,B[0]); and and2(tmp4,An1,B[1]); and and3(tmp5,An0,B[1],B[0]); or or_ ALTB (ALTB,temp3,temp4,temp5); // A greater than B output and and4(tmp6,Bn0,Bn1,A[0]); and and5(tmp7,Bn1,A[1]); and and6(tmp8,Bn0,A[1],A[0]); or or_AGTB(AGTB,tmp6,tmp7,tmp8); assign A_greater_B = tmp6 | tmp7 | tmp8; endmodule 5. a. Instantiate the module comparator from question 4 and call it Comp1. Connect the ports by ordered list. module comp1_a ( x, y , equal, greater, less); input [1:0] x,y; output equal, greater, less; . comparator Comp1 ( x , y , less,equal , greater); . <stimulus> .
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