lab03

Detail 2-bit quantization ?

For a microprocessor similar to ATmega328p an 8 bit ADC uses a VREF = 3.3 V. When an analog read is executed the return value is 112. What Voltage is present on the input? Enter the value in the box provided in mV. Round to the nearest mV.

Q4) Design a Register File which includes four 2-bit registers (In total, it includes 8 bits). Each register is named as ala0, b1b0, c2c0, d1d0. Registers are loaded from the S input. In addition to that, there are two input signals, X and Y, to determine which register to select (ie. 00 selectsfirst register ala0 etc). Also there is R signal. When W is zero, the content of the register does not change. When the W is 1 the selected register is loaded with a new value by shifting from the S input. Design this register file by using D flip-flops.

Include circuit diagram

Plz I need the answer of this question in digital system design

Please write nicely.    Draw the 4-bit shift right register circuit implemented with JK type F/Fs. Since the circuit has serial data inputs (01101011), what will be the Q outputs of the F/Fs at the end of the 5.CLK? (F/F outputs are 0 at the first time, show each step in the table.)

2. Latch/FF/register design. (a) Design a SR-latch with enable using a D-latch and gates. (b) Design a D-latch using an SR-latch and gates.

Assume the values yourself and solve it please

Let A = ajao and B = b¡bo be two-bit binary numbers. A and B can take on values from 0 to 3 (for example, A = 2 when a1ao = 10. Let C be a two bit binary number whose value equals the magnitude of the difference A – B. We have C = c1c0 = |A – B|. (This means that if B is larger than A then you consider B-A.) You are to design a circuit which accepts A and B (i.e., a¡ aob¡bo) as inputs and outputs the result C = c¡c0. The circuit thus has four inputs and two outputs. For example, the circuit should output c1co = 10 when ajao = 01 and bibo = 11 (C = 2 when A = 1 and B = 3). - Your pre-lab needs to include all items requested in the following steps (plus those requested in the pre-lab handout): 1. After reading through the complete lab, write a description of the expected behavior of the system you will design. 2. Draw a truth table describing the behavior of the circuit. The truth table should show the inputs: aj aobibo (in this order) and the outputs: c1Co · 3. Write the canonical SOP…

What is edge triggering?

Implement 32-Bit MIPS Register file (Zero Register…etc)   Information in Image

4) Write the function table for the given 1-bit ALU in the figure. Ainvert Binvert LO B invert Carry in (MUX) Carryin CarryOut Operation Operation (MUX) Result AND OR ADD SUB NAND NOR Result

Each instruction below

(b) For a two-input EX OR gate, Find the standard SOP and POS expressions as a function of input variables.

Up/Down State Machine Cousider a state machine implementation of a two bit up/down counter mput: up/doun, and two outputs: Outo and Out,, which also indicate the next state. When up/dowTI is high, the counter counts up (00,01,10,11,00, ). When up/doun is low, the counter counts down (00,11.10.01.00, ..). The state machine has one Part A Complete the state diagram below by adding all required transition arcs with input annotations. Output annotations are not required since they correspond to the new state. state state 00 01 state state 10 11

Define components and write a VHDL description of the circuit defined in "Using primitive gates, write a Verilog model of a circuit that will produce two outputs, s and c, equal to the sum and carry produced by adding two binary input bits a and b (e.g., s=1 and c=0 if a=0 and b=1)." .

(b) For a two-input OR gate, Find the standard SOP and POS expressions as a function of input variables.

Correct and detailed answer will be Upvoted else downvoted. Thank you

Use Verilog to design an FSM. The FSM accepts an input binary sequence such as 001010011101.... Its output is zero except when the number of 1's that have been input is a multiple of three. In the example below, the output that is observed after each input bit is received is shown directly below the input bit received: input : 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 output: 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 0 1 Note: Before any bits have been received, the output is 1. This is because zero 1's is also a multiple of three. Materials to be submitted: 1. Verilog codes for FSM module. You can choose either two-always or three-always blocks style. 2. Verilog codes for testbench using the above example 3. Image of the screen that shows the test results.