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Tran, Ngoc Tran
CPE/EEE 64L - section 8
Professor RK
11.24.2023
Lab 03: Sequential Logic 1
Title:
Sequential Logic: Latches, Registers, Flilp-Flops, Adders & Comapators Objective:
This lab is about becoming familiar with the circuit board, using the switch as input to light up
the LEDs. Use basic knowledge learned about Boolean and table truth to analyze and
implement logic circuits. Learn how to create schematics and logic diagrams through MultiSim.
Also get familiar with verilog and learn how to use Quartus II program to write the structural
modeling and create a waveform for the circuit and demo it to Professor. Lab Preparation and Challenges:
1. USB 10M50DAF484C7G.
2. Listen to the instruction of the Professor.
3. Practice to create files and code in Quartus. 4. Build the Multisim demo.
5. Know how to read and use the truth table and K-map to implement a logic circuit. 6. Understand a logic in a circuit, know how to solve its equation. 7. Read the tutorial for Quartus and waveform programs. Lab Results (Engineering data):
1. Part 1: Four-bit adder circuit DemoAssignment
My constant number is B which is 11= 01011. In this lab I was given a constant number that
would be used throughout the whole lab. In this section I was asked to design a verilog program
that used to test the four-bit adder circuit. That means my program has to add my constant
number to the range of numbers from 0 to 15. I used the knowledge taught in the discussion to
add BCD (binary code decimal) numbers together and came up with the truth table for my
program. The image below shows my truth table:
After getting the truth table, I started using K-maps to write down the equations - including 5:
S4, S3, S2, S1, and S0. The equations will be used to design my verilog program. This is a display
of the equations I got from K-maps:
Before designing a program, I built a logic diagram for 5 equations using multisim. I used more
than 14 gates including an and gate, not gate, or gate, switches, LEDS, and resistors to be able to
create a logic diagram that works for my program. My inputs in the truth table and logic
diagram are A, B, C, D and my outputs are S4, S3, S2, S1, S0 respectively. Here is my logic
diagram: And that is all I need to do for part 1, build a solid foundation including truth tables, equations
and diagrams to be able to design verilog programs.
2. Part 2: Four-bit adder Verilog DemoAssignment
3. Part 3: Full four-bit adder DemoAssignment
4. Part 4: Design of Comparator Using Gates DemoAssignment
5. Part 6: Design a 3-bit comparator Signed and Unsigned Switch DemoAssignment
6. Part 7: Special Design DemoAssignment
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Related Questions
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The numbers from 0-9 and a no characters
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True
In a (CA) method of 7 segments, the
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* "connected to the logic "O
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* .with shift registers
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i)
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(c)
Figure Q3(c)(i) shows a register and Figure Q3(c)(ii) shows the input waveforms
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A1
A9
A10
A2
Function generator
A3
A11
A12
AS
A13
A6
A14
A7
A15
Data in
Bop.7)
ip.r
82p.7)
Logic analyser
U1
U2
U3
U4
UO
6.
1.
6
1
6
INVERTER
3
CLK
3 CLK
oCLK
CLK
5
K
K
5
K
K
4027
Clock
Function generator
Figure Q3(c)(i)
(i)
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B
X
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