Lab 2

Figure 1 shows a layout implemented in the 45 nm CMOS process described in the information sheet (n+implant and p+implant layers not shown). Process parameters, device equations, layer key and design rules can be found on the information sheet. P-WELL VTG VTL X A B ++++++++++ Onm 100 200 Figure 1: Circuit layout. Drawn to scale.

Consider a digital logic circuit with two diodes as shownin figure 1. The diodes D1 and D2 are ideal (i.e. Vy = 0). 12 D ov, out 10 D2 5V 50kO Figure 1 A digital logic circuit with two ideal diodes A. Complete the equivalent circuit below and determine the output voltage vout oV and v, = 5V. Verify the conduction states of diodes by finding the current through D, and the voltage across D, when vị = Note that the output voltage is the same when v, = 5V and v, = 0V. 12 D out 12 D2 5V 50k2 Complete the equivalent circuit below and determine the output voltage vout when vị = v2 = В. 5V. 1Ω D Qut 10 5V 50k2 B.

Solve this Question in a very detailed form to help with understanding of the question. Please answer in steps.

1. Moore's Law: 1) What is Moore's Law about? 2) Why we have been used Moore's law to predict computer performance before multicore? 3) What limits the performance scaling based on Moore's law

draw the cmos diagram for the following equation ((A +B)’+C)’ * (D’ E’ +F)’