IT 105 HW9

Construct an nmos circuit with depletion load with the function  parameters are VDD = 5 V VTND = 0.4 V, VTNL = -0.6 V, (W/L)_L =1 Determine (W/L)_d of each transistor where output vo  is 40 mv

Answer the following questions i. ii. What is address depletion problem in IP v4 ? Due to what causes does this problem arise? ii. What are the possible solutions for such problem?

Please provide Handwritten answer

I want presentation about mosfet / Jft

**Without Explain Please ****Without Explain Please ****Without Explain Please ** 1. When a press switch is connected to VDD one side and the other to the mid of two resistor as voltage divider which one end to the ground and the other goes to P3 is called.. a.Not activeb.Active highc.Active low 2. In the AVR ATMEGA16 the structure of the IO/p ports includes … a.1 ADCb.8 ADCc.2ADCd.4 ADC 3. The sketch for AVR ATMEGA16 when connected to an LED PORTD |=(0x01<<0) means a.Turn on PC1b.Turn off PC0 1c.Turn on PC0 d.Turn off PC1 4. The sketch for AVR ATMEGA16 statement if((PINC &(0x01<<2))==1) means a.Wait for PINC1 to be logic 1 b.Wait for PINC1 to be logic 0    c.Wait for PINC2 to be logic 0. d.Wait for PINC2 to be logic 1 5. The sketch for AVR ATMEGA16 statement PORTB &=~(0x00<<1)means    a.Turn on PB1b.Turn off PB0c.Turn off PB1 d.Turn on PB 0 **Without Explain Please **

4) Describe cell phone standards and systems such as FDMA(AMPS/TACS), TDMA (GSM/IS-54) and CDMA (IS-95).

Write TRUE if the statement is correct but if it’s false, change the underlined word or groupof words to make the whole statement correct. The subject is basic electronics. please answer my questions. thanks

Suppose that we have an unusual type of FET for which iD=3vGS3+0.1vDS Here, iD is in mA, vGS is in volts, and vDS is in volts. Determine the values of gm and rd for a Q point of VGSQ=1 V and VDSQ = 10 V.

To implement 8-to-1 line multiplexer using two 4-to-1 line multiplexer(MUX): O a. The third selctor is connected to the enable line of the first and second MUX. O b. Only the enable line of the first MUX must be connected dirictly to the enable for the second MUX. O c. The third selctor is connected to the enable line of the first MUX which is connected through inverter to the enable of the second MUX. O d. All inputs lines for the first mux must be connected to the input lines for the second mux.

Using NAND gate design NOT, AND and OR gate

Q.2) What is the method of arbitration of the PCI bus? Modify the following diagram arbitration, when there is a device C request use the PCI bus at the same time with device B. The arbiter services the device A then C to transfer 2 data for each, then service device B to transfer 1 data. CLK REOA REQ-S %3D GNTEA GNT-B %3D FRAME %3D %3D IRDY %3D TRDY Address Data Addre Data AD

As compared to N-channel MOS switch, the P-channel MOS switch has _____.   a.more ON resistance b.equal ON resistance c.either 'a' or 'b d.less ON resistance

Are the following statements correct or wrong? Justify your answer. (a) GTO requires very high current applied to its gate to be turn ofr. (b) IGBT is a current driven device. (c) IGBT is more efficient than BJT in high power applications. (d) Thyristors are used only for low voltage, low current applications. (e) MOSFETS are used for low frequency applications.

a) Calculate the value of IDb) Determine VDSc) What effect has the insulated channel from the gate in MOSFET? (summarize your answer in less than 10 words only)   Please answer in short like it definitely don't reject in shorts please  It is completely  question..   ..

The ______ terminal of the JFET is the equivalent of the Collector terminal of a BJT. a.Drain b.Source c.None of these d.Gate

Consider that we have a component of the full adder type, as illustrated in the figure below.Make the structural description in VHDL of an 8-bit adder using 8 components that are 1-bit full adders described as in the figure above.

VLSI Wafer Yield  Given the defect density D= and chip area A, use Murphy's yield model to estimate the chip yield. Calculate for D=0.5 defects/cm2 D=0.5 defects/cm2 and A=1.5 cm2 A=1.5 cm2.

The parameters of the transistor below are VTN = 0.6 V and Ka = 0.5 mA/V?, find the value of R1, R2, Rp such that IpDQ = 0.5689 mA, VDSQ = 1 V and R1+R=90 k2. Sketch the load line and plot the Q-point. v*= +2.5 V Rp R R2 V---2.5 V ww

Fill in the following blanks. Only use one word for the blank space. Metal atoms are implanted into the active areas of NMOS transistors. atoms are implanted into the n-well of CMOS. is used for gate terminal of NMOS transistors. are used to connect poly and metal layers.

The ______ terminal of the JFET is the equivalent of the Emitter terminal of a BJT. a.None of these b.Source c.Gate d.Drain

UTM & UT &UTM & UTM 3 UTM & UTM & UTM &UTM & UTM (a) Figure Q.la shows the connections of all subsystem in one complete system. (i) Draw sionTM" & UTM & UTM (ii) Reduce the blocks diagram into a single transfer function of UTM C(s) R(s) &UTM ITM R(s) flow graph of the system. UTM G₁(s) + G₂(s) TM & UTM, H₁(s) H3(s) Figure Q.la H₂(s) G3(s) G₁(s) C(s) & UTM & UTM & UTM 3 &UTM 3

Homework 8 (1) A two-level VSC with the switching frequency 6kHz, the AC line frequency is 60Hz, find the two lowest frequency harmonics. (2)An MMC circuit with 201 units in each arms, find the levels for phase output voltage and line output voltage. (3)Make comparison of the properties of VSC and LCC as inverters.

Question 5: a) In the context of WCDMA, answer the following questions: What is the chip rate of WCDMA? i. ii. What is the duration for WCDMA frame? iii. For the figure shown below, what is the spreading factor? Symbol iv. V. vi. vii. Data Spreading code Spread signal Datax code Spreading What is the corresponding processing gain? For the figure shown below, what is the multiplexing mode used? Uplink Downlink Frequency Time WCDMA has a frequency reuse of 1 between different cells. What does that mean? If fast fading occurs when the path difference between two received signals is half wavelength. Calculate the path difference at a frequency equals to 2 GHz.

FET Construction 1. In the depletion type MOSFET there are two modes of operation : 1 2 2. In an n-channel enhancement type MOSFET if VGS = OV and VDS > Ov then ID >0 A. a) True. b) False. (if false correct the answer) 3. When a negative potential is applied to the gate terminal of a depletion type MOSFET transistor, the number of free carriers at the channel are 4. In an n-channel depletion type MOSFET consider the situation if VGS is kept constant and Vos is increased. Explain briefly what will happen to the channel if Vos is increased further. 5. In an n-channel enhancement type MOSFET if VDs ≥ VGS - Vth and VGS Vth then Ip 6. In an enhancement type MOSFET if: a) VGs > Vth and Vos = Ov then the shape of the channel is b) VGS > Vth and VDs > Ov then the shape of the channel is 7. In an n-channel depletion type MOSFET V, is a p-channel depletion type MOSFET V₁ is while for

What are MCBs? Explain the working also?

Modified True or False The subject is basic electronics. please answer my questions. thanks

2. (1) Prove that NOR gate is equivalent to a negative AND gate by constructing a simple circuit using NOT and AND gates and verify the truth table experimentally. (Note: Use 7404 and 7408 ICs) (ii) Prove that NAND gate is equivalent to a negative OR gate by constructing a simple circuit using NOT and OR gates and verify the truth table experimentally. (Note: Use 7404 and 7432 ICs)

Fill in the blank. 1. The _________ can actually be used as a voltage-controlled resistor because of a unique sensitivity of the drain-to-source impedance to the gate-to-source voltage.2. The ________________ for any JFET is labeled IDSS and occurs when VGS = 0 V.3. The relationship between the drain current and the gate-to-source voltage of a JFET is ______________ as defined by Shockley’s equation. As the current level approaches IDSS , the sensitivity of ID to changes in VGS increases significantly.4. A ______________ device employs a unique combination of a p-channel and an n-channel MOSFET with a single set of external leads.

Explain each of the following topics: III. Describe cellular standards and systems (FDMA, TDMA, CDMA).