Module5_Questions

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Worcester Polytechnic Institute *

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3829

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Electrical Engineering

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Dec 6, 2023

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pdf

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6

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Module 5 Questions 1 Module 5 - Lecture 18 (2/16/23) (Thursday) 1. Describe the Design Flow for creating a Block Design with an Embedded processor with a couple AXI peripherals added? 2. When a MicroBlaze is included in the Block Design, what modules are automatically generated? 3. What functionality does the AXI Interconnect block provide? 4. Implementing an FPGA design with an MicroBlaze processor has its advantages but what are the costs and design trade-offs of adding a MicroBlaze? 5. When using a processor embedded in an FPGA, the designer has a choice of where to implement certain functionality. There is a division of labor between FPGA logic and microprocess. What should go in FPGA logic and what should be implemented in the microprocessor.
Module 5 Questions 2 Module 5 - Lecture 19 (2/17/23) (Friday) 1. The design is using an AXI4 Timer configured to increment by 1 on every CPU clock tick. The CPU is running at 100 MHz. ALS sample must be taken every 5 usec. What is the target count to achieve this sample rate? 2. In the polling loop below what is our loop delay in nsec? Our CPU is running at 100MHz. 3. The start_sampling function in question 22 is implemented below. a. The design uses the AXI4 Timer configured to increment by 1 on every CPU clock tick. b. The clock is 100 MHz c. The target count is set for 5 uses sampling rate. d. Last_count is the count at the last time data was sampled. e. Current_count is the current timer value. For the maximum loop delay in question 22, what is the worst-case sampling rate error? Assume that the loop delay has some small variation.
Module 5 Questions 3
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