lab 11

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University of Texas, Rio Grande Valley *

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2401

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Electrical Engineering

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Dec 6, 2023

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pdf

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Experiment 11 Introduction: Memory elements are used in computer memory and, more broadly, in sequential circuits. Any smallest portion of such a system that has more than one stable state is referred to as a memory element. A binary shift register, for example, has four flip-flops and 16 states, but each of its four memory elements has just two states; a ternary shift register, on the other hand, has 81 states but still has four memory elements, each with three states. It differs because combinational logic cannot remember, output logic values are functions of inputs only Feedback is needed to be able to remember a logic value, memory elements are needed most digital logic circuits to hold (remember) logic values, 2 basic types of memory element. There are latches; Level-sensitive inputs and Flip-flops: Edge-triggered on active edge of clock. Procedure: 1. The circuit on Figure 1 is built and tested by following the sequence on Table 1, from top row to bottom row. 2. The values for Q and Q’ are filled out. 3. The circuit on Figure 2 is built and tested by following the sequence on Table 3, from top row to bottom row. 4. The values for Q and Q’ are filled out. 5. The circuit on Figure 4 is built and tested by following the sequence on Table 5, from top row to bottom row.

6. The values for Q are filled out. 7. The circuit on Figure 6 is built and tested by following the sequence on Table 7, from top row to bottom row. 8. The values for Q are filled out. 9. The master-slave D flip-flop is demonstrate to the instructor. Results: This experiment contains multiple parts covering memory elements. Part one covers the basic SR latch. This latch contains two NOR gates that wire into each other’s input. As for the other inputs, there is a reset and a set input. The set input will create an output of one if it is active. The reset input will create an output of zero if it is active. The purpose as to why the output of the gates are wired into each other is to create a sort of a memory function. This means that the latch will remember the output from the previous state. For instance, if the output was one from the previous state, and reset is active in the current state, this will make the output zero. Another example would be if the output from the previous state was one, and both inputs (set and reset) are inactive in the current state, the output would still be one because it hasn’t been reset. In other words, setting both S and R to low would result in no change to the output Q. If no change occurs then the current output is the previous output. When the inputs S and R are equal to one, then the output will be invalid. Part two of the experiment covers the gated SR latch. In order to build this latch, it would need to contain four NAND gates. The difference between a gated SR latch and a basic SR latch, is that a gated latch includes a Clk input. The input signal Clk affects the output Q based on if it is either

HIGH or LOW. If Clk is HIGH, Q changes according to the input of S and R. If Clk is LOW, the output will retain its previous value. Part three of the experiment covers the gated D latch. To build this latch, an SR latch would need to be built first. There are two inputs for the gated D latch, D and Clk. The D input would connect to the S input. Clk would connect to the Clk input. Lastly, the input of R from the SR gate would connect to NOT D. For this kind of latch, the definition would be: When Clk is HIGH, Q(t+1) is equal to the binary value of D. When Clk is LOW, Q(t+1) is equal to Q(n). In other words there is no change. This would be the summary of how the output Q would behave in response to its inputs, Clk and D. The final part of this experiment, part four, covers the master-slave D flip flop. In order to build this flip flop, two gated D latches are needed. The schematic is important for this flip flop because it is more complex compared to the other latches. Its complexity comes from the combination of latches that were covered in previous parts. The first gated D is the master component. Its inputs are the same as they would be for a gated D latch. For context, D connects with D and Clk connects with Clk. The second gated D latch is the slave component. The D input is the same as the master component but the Clk has the input of NOT Clk. The main difference between a gated D latch and a Master-Slave D flip-flop is that a gated D latch changes its output as long as Clk is HIGH. However, the Master-Slave D Flip-Flip proforms differently. For instance, when Clk is HIGH, the master stores the value of D. When Clk is LOW, it produces a steady output of what was stored. In order to verify our data for this experiment, the Master-Slave D Flip Flop was demonstrated using the truth table. It is important to note that the circuit needs to be reset so that it starts off with its default settings. Also the process would need to follow a certain order because these

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