ALUwithMultiplexerLab

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Full Sail University *

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COD3412

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Electrical Engineering

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Apr 3, 2024

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docx

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Turn-in sheet Multiplexer Design The multiplexer (MUX) is a device that acts as a multi-position switch. See Figure 1. A number of DATA inputs are applied to this device (D0-D3) and one of the inputs is switched to the output (Y) of the device. A binary number applied to the SELECT (S1 & S0) lines controls w YourNameMuxALUlab hich input is passed to the output. For example, when S1=S0=0, D0 is connected to the output Y. When S1=0 & S0=1, D1 connects to Y and so forth for D2 & D3 to connect to Y. Notice that the inputs, S1 and S0, and the output, Y, are active-low. YourNameMuxALUlab Instructions Draw a truth table for the 4-to-1 multiplexer Write the Logic Equations for the multiplexer Design a circuit for this multiplexer using the NOT, AND, and OR gates as components Write a test-bench to verify the operation of the multiplexer. The test-bench should try different numbers values that simulate the behavior. Deliverables Submit the circuit schematic, iSim waveform, and test-bench Arithmetic Logic Unit An arithmetic and logic unit is a combinational logic circuit capable of performing several arithmetic and logic functions, selected by a set of function-select inputs, on a pair of n-bit operands. Assume the data to be active high for this experiment.
Instructions Design and build a 4-bit ALU using only the four supplied 4-bit bus models and Xilinx's 4-bit adder/subtractor (ADSU4). The ALU's required operations and Multiplexer selection truth table is displayed above. The MUX is used to select which operations to be outputted from the A.L.U. has three inputs labeled with SEL. Use 4-bit buses to connect logic gates (std_logic_vector(3 downto 0). Hints Review Lecture notes To find the complement of A, review the 4-bit Adder/Subtractor lab Avoid using Vcc and GND to drive logic values Use merged nets Sample 4-bit ALU Adder Test Bench (NOTE: only one line of the truth table) InputOne<="1100"; InputTwo<="1010"; Sel<="101"; ADD<=’1’; CI<=’0’; wait for 10 ns; Turn-in sheet Deliverable Correctly add the six parts (5 different parts) onto your schematic drawing -10 pts Create a Bus that connects these parts -5 pts Generate the correct testbench -5 pts Correct ALU Output: Bus Complement of A -10pts
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