A LOW POWER BIST TPG FOR HIGH FAULT COVERAGE AND
Mayank Chakraverty, Ritaban Chakravarty, Vinay Babu, and Kinshuk Gupta
Mayank Chakraverty is with the Semiconductor Research & Development Center, IBM, Bangalore, India (e-mail: email@example.com).
Ritaban Chakravarty was with New Jersey Institute of Technology, NJ, USA (e-mail: firstname.lastname@example.org).
Vinay Babu is with Invntree, Bangalore, India (e-mail: email@example.com)
Kinshuk Gupta is with the Indian Space Research Organization (ISRO) Satellite Centre, Bangalore, India (e-mail: firstname.lastname@example.org)
Abstract¬¬¬- This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST. BIST is a device, here part of the functional device is self dedicated to self-testing the correctness of the device. In general BIST is comprised of two TPGs: LT-RTPG (Low Transition-Random Test Pattern Generator) and 3-Weight WRBIST(Weighted Random Built In Self Test) Minimization of hardware overhead is a major concern of BIST implementation. In test-per-scan BIST, a new test pattern is applied to the inputs of the CUT every m + 1clock cycles, where m is the number of scan elements in the longest scan chain. By using two proposed TPG increasing fault coverage is achieved through the reduction of switching activity, thereby dissipation of power is minimized.