A Novel Design Of A Double Tail Comparator

2400 WordsSep 15, 201410 Pages
A Novel Design of a Double Tail Comparator . P. satish babu/M.Tech student Department of ECE VLSI&ES Machilipatnam, India p.satish605@gmail.com Abstract :A new CMOS clocked dynamic comparator using two input single output differential amplifier as latch stage suitable for high speed analog to digital converters with the performance of high speed, low power dissipation and low immune to noise. The conventional dynamic comparator requires more power and has more delay. A conventional double tail dynamic comparator consumes less power and works at high speed than its predecessor, the conventional comparator. There is very much need to reduce the delay and power consumption which is possible by strengthening the positive feedback during the regeneration. This can be achieved by adding few transistors to the double tail dynamic comparator. Using the inverter based differential amplifier to design a novel double tail comparator for reducing the no of transistors and better characteristics. The performance of this method is to be analyzed with the existing two designs at different power voltages and frequencies using 0.18μm CMOS Technology. Key words: Double-tail comparator, dynamic clocked comparator, high-speed analog-to-digital converters (ADCs), low-power analog design, inverter op-amp. 1. INTRODUCTION Comparators also known as single bit analog-to-digital converter that are mostly used in abundance A/D converter. A CMOS dynamic latched dynamic comparators are provide low

More about A Novel Design Of A Double Tail Comparator

Open Document