Computer Engineering : A New Class Of Power Conscious Cad Tools Essay

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Navjeet Singh / March 15, 1995 / Applying for MS – Computer Engineering - Fall '17, The Bradley Dept. of ECE STATEMENT OF PURPOSE I could either watch it happen, or be a part of it – Elon Reeve Musk
To meet our growing technological demands – Electronic Chips must be designed to be more powerful and efficient as they shrink. However, is there a limitation to it? – A naive me pondered 3 years ago. In today’s world, Energy efficiency and performance have become the primary focus; an era where low-power dissipating microelectronic circuits are required for battery-operated applications while maintaining computational throughput. A multifaceted approach which includes – employing better design techniques and development of a new class of power conscious CAD tools should be employed with a goal to design low power circuits having an optimum power-area-delay trade-off.
Although my academic parameters and merit-based Prime Minster scholarship indicate strong academic performance, what defines me is my constant yearning to learn by going beyond the required curriculum through active participation in various technical events and seminar. During my sophomore year, I was introduced to the field of VLSI design while working in IEEE Electronics and Robotics Special Interest Group through a seminar on the topic “The Death of Moore’s Law will spur innovation”, predicting the rise in performance of FPGAs
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