preview

DIGITAL DESIGN THROUGH VERILOG

Satisfactory Essays
Open Document

www.jntuworld.com

Code No: L0422
Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.Tech. II Sem., I Mid-Term Examinations, Jan/Feb – 2011
DIGITAL DESIGN THROUGH VERILOG
Objective Exam
Name: ______________________________ Hall Ticket No.
A

Answer All Questions. All Questions Carry Equal Marks.Time: 20 Min. Marks: 20.

I

Choose the correct alternative:

1.

Verilog HDL is used to model
A) An Analog System
B) A Digital System

2.

3.

C) A Discrete System

[
]
D)All the above

Which of the following is not an white space character
A) \t
B) \n
C) \b

D) \s

$stop is used for
A) break point

[
D) terminate the program

B) start point

C) initial point

[

D
L

R
O

]

]

4.

To provide interface by which a module can …show more content…

10.

J

C) A Discrete System

[
]
D)All the above

Which of the following is not an white space character
A) \t
B) \n
C) \b

D) \s

$stop is used for
A) break point

[
D) terminate the program

B) start point

C) initial point

[

Cont……2

www.jntuworld.com

]

]

www.jntuworld.com

Code No: L0422

:2:

Set No. 2

II

Fill in the blanks

11.

To represent physical connection between structural elements __________data type can be used.

12.

Implicit continuous assignment of delay can be used in ____________ modeling.

13.

Sequential blocks in behavioral modeling are specified with __________, _________Keywords.

14.

Delay associated with a gate output transition to a ‘1’ from other value is called _________delay.

15.

__________is used to verify design in real-life environment with real system software running on system 16.

Delay associated with a gate output transition to the high impedance value (Z) from other value is called ____________

17.

Event based timing control is possible with _____________modeling

18.

In Verilog, with respect to gate delay’s, which delay is the minimum of all delays ___________

19.

Process of converting a high–level description of design into an optimized gate level representation is called _____________

20.

Delay associated with a gate output transition to a ‘0’ from another value is called __________

D
L

R
O

W
U

J

T
N

-oOo-

www.jntuworld.com

www.jntuworld.com

Code

Get Access
Related
Get Access