Delta Sigma Linear Processing Circuits

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3 Research Objectives
3.1 Research Objective 1: Delta-Sigma Linear Processing Circuits

The goal of this research objective is to analyze the performance of Delta-Sigma linear processing circuits, including adders and coefficient multipliers. Examples of questions that we wish to address include the following. What is the noise shaping performance of high-order digital Delta-Sigma modulators for Delta-Sigma adders? What is the frequency response of Delta-Sigma coefficient multipliers? What is the circuit power and area of Delta-Sigma MAC circuits compared to conventional circuits?

3.1.1 Background and Rationale

Multiply-and-accumulate (MAC) are fundamental linear operations in signal processing. However, they also represent a bottleneck in mobile signal processing systems insofar that the circuit complexity and power consumption of conventional digital adders and multipliers are relatively high whereas mobile systems need to be miniaturized and power-efficient. Although alternative MAC circuit structures have been proposed, their performances do not yet meet the demand of applications that require intensive computing operations with limited battery power [34]. A Delta-Sigma based MAC, therefore, constitutes a promising solution for low-power DSP devices.

Delta-Sigma based MAC circuits use Delta-Sigma bit-streams as their input and output. For instance, the inputs of a Delta-Sigma adder are digital bit-streams generated by Delta-Sigma Modulators. The adder also produces
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