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Design Automation Of Integrated Circuits And Fpga

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ECE 501 Home Work Assignment Instructor: Eric J. Balster. Student: Modukuri Sri Harsha

INTRODUCTION:
VHDL – VHSIC HARDWARE DESCRIPTION LANGUAGE is a hardware description language used in design automation to describe signals in integrated circuits and FPGA’s. This is used to write codes for the circuits and it is simulated. The test for the codes is done in the ALTERA. The Simulation models are called as test bench. This Test bench is to verify the functionality of the …show more content…

In this we create a binary file that can program the DE2 board FPGA. Connect the power to board and board to laptop through USB Blaster port. Here we finally test the design on FPGA.

Types of Execution: Here in this VHDL coding there are two types of executions that are used in it. Dataflow type and Behavioral type. The Dataflow is executed using the Boolean expressions and the signals that are given as inputs and outputs. In Behavioral type processing of signals takes place inside the statement. In this signals are simulated in sequential order.

Designs: For F3: 00 01 11 10

1

1

1

1 1 1 1 1 1

00 01 11 10
From the above table we have 1 quad label and 4 pairs,
On solving the above K-Map we get an Boolean equation for the input A,B,C,D is given by F3: B’C+A’B’D’+BC’D+A’BD+ACD’

For F2: 00 01 11 10

1

1

1

1 1

1

1

1

1

00 01 11

10

From the above table we have 1 quad label and 1 pair and 4 singles,
On solving the above K-Map we get a Boolean

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