Disadvantage Of Vedic Multiplier

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Abstract—Theperformance of system is directly proportional to throughput of the multiplierhence multipliers are effective in many applications. The system depended throughput of multiplier and a system became slow therefore we need to design high performance multiplier. In this paper we implement The Vedic Multiplier and the Reversible Logic Gates and Accumulate Unit (MAC) UrdhavaTriyagbhayam sutra for design of Vedic multiplier and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. . The analyses result shows that our multiplier is faster than conventional multiplier and compares delay required for multiplier operation and also compare…show more content…

The Vedic mathematics applicable over complex calculation, it reduces the typical calculation into a very simple one. This is so because the Vedic formulae are claimed to be based on the natural principles on which the human mind works. Vedic Mathematics is a methodology of arithmetic rules that allow more efficient speed implementation. It also provides some effective algorithms which can be applied to various branches of engineering such as computing.

1) UrdhvaTiryakbhyam Sutra

The Vedic multiplier is depends on the “UrdhvaTiryagbhyam” sutra (algorithm). These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system. In this work, we apply the same ideas to the binary number system to make the proposed algorithm compatible with the digital hardware. It is a general multiplication formula applicable to all cases of multiplication. It literally means “Vertically and Crosswise”. It is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products. The algorithm can be generalized for n x n bit number. Since the partial products and their sums are calculated in parallel, the multiplier is independent of the clock frequency of the processor. Due to its regular structure, it can be easily layout in microprocessors and designers can easily circumvent these problems to avoid catastrophic device failures. The processing power of multiplier can easily be increased by increasing the input and output data bus widths since it has a quite a regular structure. Due to its regular structure, it can be easily layout in a silicon chip. The Multiplier based on this sutra has the advantage that as the number of bits increases, gate delay and area increases very slowly as compared to other conventional

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