# Fault Current Reduction By The Design Of Pid Based Fcc

2029 Words9 Pages
2. Fault Current reduction by the design of PID based FCC Considering the increasing popularity of DGs, it is certain that large deployments will take place in the near future. The fault current flowing through the power line should not exceed the rating amounts of the system which is expressed as the following condition (1) The fault current flowing from bus i to j caused by a bus f can be calculated by the following expression (2) Where is the i-th bus voltage, is the j-th bus voltage, is the f-th bus voltage, is the impedance of the i,j-th line. And (3) If the fault current build up might reach a value higher than the ratings of the protection devices brings the need to design a novel PID based FCC which is explained in the following section. FCC is a variable impedance device connected in series with the circuit to limit the current under fault conditions which also has the potential to lead the lower rated components being used. The FCC is a simple LC circuit at the net frequency with a shunt capacitance that limits the short circuit current to an acceptable level. It is essential to determine the size of the FCC used in the power line which is also to be as small as possible. The existing works uses a fixed size FCC to reduce the fault current even while the fault current produced at the line is less. This leads to increase the cost of the overall system. In order to avoid such situations in this paper we propose a novel PID-FCC