Fpga Implementation Of Cyclic Redundancy Check

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FPGA Implementation of Cyclic Redundancy Check Ruijie Zhang Abstract—In the communication system, in order to reduce the error rate of the communication line transmission, error control method requires the use of high performance. Cyclic Redundancy Check (CRC) error detection has excellent anti-jamming performance in communications and monitoring. In the situation above, parallel CRC algorithm and hardware description language Verilog VHDL are adopted to realize the principle of CRC check code. Keywords- FPGA; CRC; Parallel; VHDL. I. INTRODUCTION I n the digital data communication system, due to the fact that the channel transmission characteristics are not well and noise interference, the receiving terminal receives the digital signal which to be able to have the distortion. Error code are appeared unavoidably Cyclic.Thus we must take effective measures to make the receiver can detect the error and take measure to correct. Error control code is widely used to reduce the bit error ratio. Redundancy Check is a kind of algorithm, and it can be used comprehensively in the engineering domain .Due to the strong detection capability, the encoder is easy to implement. Redundancy Check which based on the reminder of the polynomial division.When the message is received, the computer recalculates the remainder and compares it to the transmitted remainder. If the numbers do not match, an error is detected. We know that the CRC code can be divided into two types. First one is

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