Hardware Efficient Delta Sigma Linear Processing Circuits

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Abstract: This paper presents hardware efficient Delta Sigma linear processing circuits for the next generation low power VLSI device in the Internet-of-things (IoT). We first propose the P-N pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital-signal-processing circuits: the Delta Sigma sum adder, average adder, and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by Matlab simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18 µm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future miniaturized low power VLSI circuits. Keywords: VLSI, Delta Sigma Modulation, Digital Signal Processing, Adder, Coefficient Multiplier, Low-power Low-complexity Circuits. 1. Introduction Internet-of-Things (IoT) demand ubiquitous
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