Implementation of 28T 1 Bit Full Adder

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Implementation of 28T 1-bit Full Adder
OBJECTIVE:
The main objective of this lab is to implement 28T 1-Bit Full Adder with inverter as a load and calculating the rise time, fall time and propagation delays using Cadence ™ tool for VLSI design at different stop times.

PROCEDURE:

1) A new cell view is created in the library with the type ‘Layout’ and the LSW (Layer Selection Window) and LEW (Layout Editor Window) are opened.
2) The layout is created in the LEW using the ‘Create Instance’ window. In this window the library browser is opened and the parameters for the pmos and nmos are given.
3) The properties (width and length) of the nmos and pmos are given using ‘Edit Properties’.
4) The properties are as follows:
For Sum and Inverter- PMOS - width = 0.96µm, length = 0.96µm NMOS - width = 0.96µm, length = 0.96µm

For Carry in- PMOS - width = 0.96µm, length = 0.96µm NMOS - width = 0.96µm, length = 0.96µm
5) Both the pmos and nmos are connected to form the gate by using the poly layer. The ptap/ntap are created and connected to the nmos/pmos with the metal1 layer.
6) The drains of both pmos and nmos are connected using the metal1 layer.
7) The pins for Output(Y), Vdd and Vss are created using the metal1 layer while the Input (A) is created on poly layer.

Extraction of the Layout
1) A DRC (Design Rule Check) check is performed by using ‘Verify > DRC’ in the LEW. A message in the CIW displaying “Total errors found=0” indicates that all the

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