In this paper an ultra low power and probabilistic based noise tolerant latch is proposed based on Markov Random Field
(MRF) theory. The absorption laws and H tree logic combination techniques are used to reduce the circuit complexity of MRF noise tolerant latch. The cross coupled latching mechanism is used at the output of the MRF latch inorder to preserve the noise tolerant capability of MRF latch. The proposed latch is faster than the latches presented in the literature and provides low power and high noise immunity.
Hence we can achieve good trade off in terms of performance, robustness and cost. The latches are evaluated in 180nm CMOS technology. The results obtained show that the proposed latch consumes low power and highly noise tolerant.
Finally the proposed latch is applied in transmission gate based full adder circuit. In 180nm technology the proposed adder can operate reliably with superior noise tolerance and low power compared to conventional latch based full adder circuit. Keywords-Markov Random Field (MRF) latch, Markovian Property, C-element, Single Event Upset (SEU), Soft error tolerant, Root Mean Square (RMS) noise voltage.
1. INTRODUCTION
CMOS technology is approaching the nano-electronics range nowadays, but experiences some practical limits. High dynamic power dissipation and leakage current in deep submicron technologies contribute a major proportion of total power dissipation in CMOS circuits designed for
Nowadays, the major limitations on computation performance are memory access latencies and power consumption. Due to memory access latency, for instance, the recently achieved CPU clock frequency of 5.7 GHz must be constraint to the maximum access speed of off-chip
Review literature available on popular digital logic families on the topics of ‘noise margin’ and ‘fan-out’, and write an article (of about summarizing limitations on ‘interfacing’ between two different logic families.
The comparison of above three algorithms for 8, 16 and 32 bit operands with corresponding voltage and frequency are tabulated in table I
Conventional CMOS technology comes up with a lot of margins while scaling into a nano-level. So, to overcome this, several substitute technologies have been proposed as a solution. Quantum Dot Cellular Automata (QCA) technology is one such upcoming nano-technology that can be a perfect substitute of Complementary Metal Oxide Semiconductor (CMOS) due to its high speed and low power procedure in the field of nano-science and nano-electronics. Thus, QCA overcomes the drawbacks of CMOS technology and has a substantial relevance in the field quantum computation. In this paper, we give a review result of QCA in terms or hazards using digital multiplexer circuit as the base. Literary survey lacks in hazard free design. Hazards in a system are undesirable effect which creates uncertain outputs and can be avoided. This paper considers hazard in smallest ever 2:1 multiplexer. Static hazard has been looked into for both digital and QCA circuit. For both the circuits, hazard has been eliminated and given a comparative study in terms of delay and better one has been proposed. Design has been verified using simulation from QCA designer tool.
Gate Diffusion Input (GDI) logic is a low power Very Large Scale Integrated (VLSI) design technique which was introduced as an alternative to CMOS logic design. This technique is a two transistor implementation of complex logic functions; Logic functions can be designed with fewer gates. GDI provides in cell swing restoration when operated in certain conditions and use of restoration buffers. Digital circuits designed using GDI logic will have less power consumption occupy a minimum area, gate count and delay in the circuit is reduced. Because of fewer gates, there is less design complexity.GDI cell is as shown in the below figure 2.1
The mote’s size makes energy management a key component. The circuit will contain circuits, a temperature sensor, and A/D converter, microprocessor, SRAM, communications circuits, and power control circuits. Sensors work together with the IC, which will operate from a power source integrated with the platform.
R/2R ladder present a easy way to convert digital voltage/information to analog for output. The R/2R ladder needs consideration to in what way the device is stated when applying to actual applications. In the makings of R/2R ladder, output faults due to resistor tolerances are most of the time not considered
Now a days Wireless sensor network devices are getting attention from many researchers and many device developers. These are all low powered devices and these are getting popular and becoming critical part of many systems for their performance. These nodes consists of low powered microprocessors, sensors, communication chips, etc. All the aspects such as designing hardware to any protocols depends on how much power is being consumed by these devices. We are doing our analysis with Zolertia Z1 nodes. These devices are compact, low powered also they are easy to deploy anywhere and economically efficient. In this paper we are using actual experimental results in different environment. These
The sustained advancement of the semiconductor silicon based technology is the key driver of the performance enhancements and functionality expansion of the electronic devices. This extraordinary growth of the electronic devices types and functionality is imposing urgent needs of higher computational speeds, better data transmission bandwidths and
Computational methods and models. We have already generated theoretical models for synthetic oscillators that predict how queueing crosstalk can couple otherwise freely running oscillators42, 50, and slightly modified versions of these models will serve as the basis for our studies. Custom python code running delay-based stochastic simulation65 will be carried over from these prior works to run our models.
Face the loss in performances while improving the power efficiency, multiple Vdd, and multiple Vth techniques have been proposed. The gates on critical paths operate at the higher Vdd or lower Vth, while those on non-critical paths operate at the lower Vdd or higher Vth, thereby reducing overall power consumption without performance degradation.
While we will focus on coordinated circuits in this book, the properties of incorporated circuits what we can and can't proficiently put in an incorporated circuit—to a great extent decide the design of the whole framework. Incorporated circuits enhance framework qualities in a few basic ways. ICs have three key points of interest over computerized circuits worked from discrete parts:
Abstract — Using Moore’s law, we will continue to get abundant transistors which only will be limited by the amount of energy consumed. Energy efficiency can be improved to many orders of magnitude with the help of Near Threshold Voltage (NTV). There are various Design techniques required for reliable operation on a wide range of input voltage – from very low to sub threshold region. Coming to the systems designed for NTVs, they can select their modes of operation dynamically from very high performances, to high efficient energy modes and also to lowest power.
Generally, the lower a storage is in the hierarchy, the lesser its bandwidth and the greater its access latency is from the CPU. This traditional division of storage to primary, secondary, tertiary and off-line storage is also guided by cost per bit.
Also, the error confinement and the error detection feature make it more reliable in noise critical environment (H. Saha, 2006).