Low Power Noise Tolerant Latch Design

1623 Words6 Pages
In this paper an ultra low power and probabilistic based noise tolerant latch is proposed based on Markov Random Field
(MRF) theory. The absorption laws and H tree logic combination techniques are used to reduce the circuit complexity of MRF noise tolerant latch. The cross coupled latching mechanism is used at the output of the MRF latch inorder to preserve the noise tolerant capability of MRF latch. The proposed latch is faster than the latches presented in the literature and provides low power and high noise immunity.
Hence we can achieve good trade off in terms of performance, robustness and cost. The latches are evaluated in 180nm CMOS technology. The results obtained show that the proposed latch consumes low power and highly noise tolerant.
Finally the proposed latch is applied in transmission gate based full adder circuit. In 180nm technology the proposed adder can operate reliably with superior noise tolerance and low power compared to conventional latch based full adder circuit. Keywords-Markov Random Field (MRF) latch, Markovian Property, C-element, Single Event Upset (SEU), Soft error tolerant, Root Mean Square (RMS) noise voltage.

1. INTRODUCTION
CMOS technology is approaching the nano-electronics range nowadays, but experiences some practical limits. High dynamic power dissipation and leakage current in deep submicron technologies contribute a major proportion of total power dissipation in CMOS circuits designed for

More about Low Power Noise Tolerant Latch Design

Get Access