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Microprocessor Without Interlocked Pipeline Stages Essay

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III. MIPS ARCHITECTURE The accompanying outline demonstrates the fundamental architecture of a MIPS-based framework: Fig. 7. Basic MIPS Architecture Microprocessor without Interlocked Pipeline Stages (MIPS) is a RISC (Reduced Instruction Set Computing) architecture. Pipelined MIPS has five stages which are IF, ID, EX, MEM and WB. Pipelining means several operations at a time in a single data path. Pipelining system is utilized in this kind of computer architecture to enhance the performance of this processor. A multi cycle CPU comprises of countless tasks. So if one task occurs, rather than waiting for the process to finish, at the same time it starts another task in the same data path parallely without affecting the previous task. To make this happen, every part of the process is separated into different pipelined stages. So after each clock, the process is fed into next pipelined stage, triggering another operation in that stage without rearranging the past process. Thus all the stages in the data path can be utilized at the same time. This thusly can increment the throughput of MIPS. Fig. 8. 5-Stage Pipelined MIPS MIPS processor has been executed utilizing five pipeline stages, which are Instruction Fetch (IF), Instruction Decode (ID), Execution (EX), Memory access (MEM) and Write Back (WB). The isolation of these stages is achieved by special registers known as pipeline registers. The aim of these registers is to isolate the stages of the

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