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Module Nios _ II _

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module NIOS_II_CPU(clk_49, machine_clk_49, DOT_product_49); input clk_49, machine_clk_49; output [31:0] DOT_product_49; //I organized the signals this way in the hopes ofmaking them easier to read when viewing the waveform //and better show the flow of the instructions through the system. //Branch signals reg BR_49, BLT_49, BLT_exe_49; wire BR_out_49, BLT_out_49; // Fetch Stage signals reg [31:0] PC_49; wire [31:0] instruction_49; //Decode Stage Signals wire instruction_type_49, reg_write_sel_49; wire [31:0] instruction_ff_49; wire [4:0] reg_a_49, reg_b_49, reg_write_49; wire [5:0] OP_code_49; wire [31:0] immed_49, reg_out_1_49, reg_out_2_49; //Execute Stage Signals wire [31:0] instruction_ff_d_to_e_49; wire …show more content…

6 'b110100; parameter stw = 6 'b010101; initial begin PC_49 d4; end lpm_ff reg_1 // Saves Current instruction ( .data(instruction_49), .q(instruction_ff_49), .clock(machine_clk_49)); // Used ports defparam reg_1.lpm_width = Instruction_Width; //****************************Decode Stage***********************// //Decodes fetched Instruction NIOS_Decode Instruction_Decode (.instruction_49(instruction_ff_49), .clk_49(clk_49), .instruction_type_49(instruction_type_49), .reg_a_49(reg_a_49), .reg_b_49(reg_b_49), .reg_write_49(reg_write_49), .reg_write_sel_49(reg_write_sel_49), .OP_49(OP_code_49), .immed_49(immed_49), .BR(BR_out_49), .BLT(BLT_out_49)); NIOS_Register Read_Write_to_Register (.clk_49(clk_49), .read_1_49(reg_a_49), .read_2_49(reg_b_49), .output_1_49(reg_out_1_49), .output_2_49(reg_out_2_49), .write_reg_49(register_to_write), .data_write_49(output_to_write), .write_enable_49(reg_write_sel_ff_m_to_w_49)); always@(*) begin BR_49 = BR_out_49; BLT_49 = BLT_out_49; if (BR_49==1) begin PC_49 = PC_49+immed_49; end end lpm_ff reg_2 // Saves Current instruction ( .data(instruction_ff_49), .q(instruction_ff_d_to_e_49), .clock(machine_clk_49)); // Used ports defparam reg_2.lpm_width = Instruction_Width; lpm_ff reg_5 // Saves RA ( .data(reg_a_49), .q(reg_a_ff_d_to_e_49), .clock(machine_clk_49)); // Used ports defparam reg_5.lpm_width = 5; lpm_ff reg_6 // Saves RB ( .data(reg_b_49), .q(reg_b_ff_d_to_e_49), .clock(machine_clk_49)); // Used

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