NAME: - Parag Rao COURSE: -EE295 TOPIC: - 5 page report SJSUID: -008932014 LOW POWER FPGA Power

700 WordsApr 23, 20193 Pages
NAME: - Parag Rao COURSE: -EE295 TOPIC: - 5 page report SJSUID: -008932014 LOW POWER FPGA Power consumption is an important issue in modern FPGA’s. Greater performance and complexity has led to higher power dissipation per chip, while the use of deep sub-micron processes has resulted in higher static power in the forms of sub-threshold leakage and gate leakage. Heating solutions for devices with high power dissipation is expensive. If FPGA’s are to be used in portable devices, power consumption needs to be reduced. -powered applications, high power consumption may prohibit the use of FPGA altogether. Consequently, solutions for reducing FPGA power are needed. In this work, I propose a programmable dual-VDD architecture in which the…show more content…
[1] selects the polarities of logic signals to reduce active leakage power in FPGAs. [3] presents a cut enumeration algorithm targeting low power technology mapping for FPGA architectures with dual supply voltages. [4] presents a region-constrained placement approach to reduce leakage in FPGAs. Dual-VDD techniques have been proposed previously for ASICs [14, 12]. Recently, a low-power FPGA using pre-defined dual-VDD/dual-VT fabrics has been proposed in [7]. But, they have focused on reducing only dynamic power, while keeping the leakage constant. Further, they have used a fixed dual-VDD/dual-VT fabric, keeping all the routing resources at high-VDD, which limits the power savings significantly. Approach: - Static as well as dynamic power dissipation can be reduced effectively by reducing the supply voltage. Dynamic power has a quadratic dependency on supply voltage, while both sub-threshold leakage (due to Drain Induced Barrier Lowering, DIBL) and gate leakage exhibit exponential dependencies on the supply voltage. However reducing supply voltage may create problems in circuit operation. Use of dual-VDD is a well-known technique to reap the benefits of voltage scaling without the performance penalty. The timing critical blocks in the design operate on the normal VDD (or VDDH), while non-critical blocks operate on a second supply rail with a lower voltage (or VDDL).

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