VII. ALGORITHMS USED
In the following, we present three different algorithms to reduce the total power consumption. Each of these algorithms establishes a different method to process the variable precision data held in the operands buffer. In the following, the specified throughput Tp for the proposed 32 × 32 bit multiplier is 64 F (Mbits/s), where F is the multiplier’s operating frequency
A. Algorithm A
In the first algorithm, the multiplier throughput Tp = 64 F is kept constant by fixing the operating frequencies (f32−, f16−, or f8) of each precision-data group (32-, 16- or 8-bit) to f32 = F, f16 = F/2, f8 = F/4 (5)
B. Algorithm
*…show more content…*

The Pcompu_overhead is reduced due to the complete removal of voltage transitions. C. Algorithm C The aim of algorithm C is to find such an optimum for reduced power consumption. To reduce complexity, we will only try to find to minimize the dynamic power dissipated as a result of the computation. P=V2fC (9) =Cm32V2min32f32+Cm16V2min16f16+Cm8V2min8f8 (10) =Ӽ( f32, f16) (11) The comparison of above three algorithms for 8, 16 and 32 bit operands with corresponding voltage and frequency are tabulated in table I TABLE I Algorithm and its corresponding voltage and frequency BITS OF OPERANDS ALGORITHM

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