Peripheral Component Interconnect (PCI) Bus Arbiter

616 WordsJan 26, 20183 Pages
PCI Bus Arbiter 1. Introduction Peripheral component Interconnect shortened to just PCI, is an external bus used to connect external hardware bus to computer. The PCI bus does support the functions performed by a processor bus. However, PCI bus’s standardized working format is not dependent on any particular processor's inbuilt bus. Devices which are connected to the PCI bus are assigned corresponding addresses as per the processor's address space. Also for a bus master, they appear to be connected directly to its own bus. PCI supports a 64-bit bus, and it is clocked at up to 66 MHz for version 2.1. Read and write operations can be performed at a maximum data transfer rate of 132 MBPS using 32-bit data at 33 MHz. It supports transfer rates up to 524 MBPS on a 66 MHz PGI bus. These data transfer rates allow systems to perform up to the requirements the today’s high tech multimedia and teleconferencing applications which deal mainly with high quality graphics and video. The PCI host logic acts as a connecting medium between the processor and remaining part of the system. This design allows the PCI bus architecture to be independent of processor. To interface a different microprocessor, the designer should only change the interface logic in the PCI host logic so as to match with the new processor. Moreover, the PCI host logic allows bus concurrency. The microprocessor can continue with its tasks while a PCI bus master is accessing the bus. Two PCI devices can still communicate

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