Technology In VLSI Technology

Nowadays, the major limitations on computation performance are memory access latencies and power consumption. Due to memory access latency, for instance, the recently achieved CPU clock frequency of 5.7 GHz must be constraint to the maximum access speed of off-chip

The AXI protocol provides a high frequency operation to the devices without using complex bridges in the circuits. It meets the requirements of interfaces with wide range of components. The important features in AXI protocol are – It has separate address, control and data lines. The data which are not aligned in a proper way, the AXI supports to transfer them by using byte strobes. It consists of separate read/write channels to enable Direct Memory access (DMA). So that designer can communicate with DMA and internal memories

The low level and high level voltages for CMOS logic families are different than TTL logic families. The low level input voltage is from 0 to 1.5 volts and high level input voltage is from 3.5 to 5 volts. For output low logic state ranges from 0 to 0.05 volts and high logic state ranges from 4.95 to 5 volts. The noise margin is high for CMOS circuits compared to TTL one which is 1.45 volts for low and high

Digital and microcomputer applications, telecommunications, image processing, digital signal processing, computer architecture, electromagnetic compatibility and computer insights are some involved in the recent progresses in computer engineering. These fields

The comparison of above three algorithms for 8, 16 and 32 bit operands with corresponding voltage and frequency are tabulated in table I

The proposed algorithm takes n cores of different SOCs and grouped them together in different configuration of TAM width like n, 2n, 4n bit. The proposed

R/2R ladder present a easy way to convert digital voltage/information to analog for output. The R/2R ladder needs consideration to in what way the device is stated when applying to actual applications. In the makings of R/2R ladder, output faults due to resistor tolerances are most of the time not considered

By this new platform, the circuit could be modified easily and faster to form the derivative products.

The continuous scaling of CMOS technology has broadened the spectrum of applications. Complex architectures can be now realized on a single chip. The integration of existing and new technologies with CMOS extends the scope of implementation.

Abstract: Failure of Dennard Scaling has put a constraint on the number of transistors that can operate at the same time without thermal run away. The part of the chip that has to be turned off to keep the chip in safe temperature operating range is called Dark Silicon. With limited growth in chip-cooling techniques, multicore processors were used to satisfy the user’s need for performance. But even this multicore processors are currently inefficient to deliver and cool efficiently due to stunted growth in cooling technologies. But this multicore processors too are power limited, as a result multicore processing will soon hit the power wall. The recent study shows that at technology node 22nm, 21% of the chip is dark and using ITRS scaling at 8nm, more than 50% of the chip will be dark. This study analyses the promising techniques proposed to overcome the challenges faced due to dark silicon.

The object of our topic is the extended studies of I~V characteristics of VMOS with the variation of channel parameters. VMOS transistor is a type of metal oxide semiconductor transistor. VMOS is also used for describing the V-groove shape vertically cut into the sub-strate- material. VMOS, abbreviation for VMOS is vertical metal oxide semiconductor”. In a VMOS current flows from vertically upwards from drain to source. It can be mostly use in power amplification and audio switching, positive temperature coefficient and we can easily operate. It has emerged as the solutions of changing the shape of channel to give the voltage more quickly than the other transistor. We will show how we can make it more efficient and significant by changing drain to source channel shape. We want to extend the idea of VMOS I~V characteristics using other group (iii-iv) materials instead of SiO2, Si and P or changing the structure of gate, source and drain. As it is a bit costly we will try to make it cost effective and reduce the leakage current.

Mayank Chakraverty is with the Semiconductor Research & Development Center, IBM, Bangalore, India (e-mail: nanomayank@yahoo.com).

In modern era every people want to use things which is smaller in size, can have more functionality and cost. This can only possible if we can integrate more and more functionality into a single chip which helps achieve our objective and demand. To achieve this human wanting the scientists have developed a new concept that is nanotechnology. Nano implies 10^(-9) which is very small . After nano scale development, the scientists of the semiconductor had faced many challenges. The greater challenge was how to combine the Intellectual properties(IP) from various sources quickly and efficiently. These have been overcome by introducing system on chip technology which is very grooming topic in modern technology. System on chip mostly called as SOC is a best solution of combining a number on functionality into a single chip. System on chip is called as bus architecture based technology. System on chip is

Low power has emerged as a major goal in today’s electronics industry. The motivations for reducing power consumption differ from application to application. For high performance, portable computers, such as laptop and notebook computers, the goal is to reduce the power dissipation of the electronics portion of the system to a point that is about half of the total power dissipation (including that of display and hard disk).

Key words: Double-tail comparator, dynamic clocked comparator, high-speed analog-to-digital converters (ADCs), low-power analog design, inverter op-amp.