The Ripple Adder: Programming an FPGA Using VHDL Essay

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School: Architecture, Computing & Engineering
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BENG HONS Electrical and Electronic

Embedded Systems and IC Design
Andrew Chanerley

Assessment Deadline: 08/May/2013
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Component Number: 001
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I confirm that no part of this assignment, except where clearly quoted and referenced, has been copied from material belonging to any other person e.g. from a book, handout, another student. I am aware that it is a breach of UEL regulations to copy the work of another without clear acknowledgement and that attempting to do
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Once processed at 120 ns, Cout1 is produced without being included in the second block, making all the numbers produced by the blocks after it, wrong as well. Figure 2.2 – Block diagram of the state of the 4-bit ripple adder at time 130 ns after system start


That is, of course, until time 129.99 ns,where the second block now “sees” the new value of Cout1 and so processes it, changing the final result into 20 (10100B) as seen in figures 1.1 and 2.2 (time 130 ns), which is also an erroneous answer.
This is due to the same reason as in figure 2.1. The Cout2 of the second block does not exist at the time the third and the rest of the blocks are processing the applied inputs (time 129.99 ns).
This phenomenon also occurs for the third block at time 140 ns, until the final result is obtained at
150 ns, where the correct answer 24 (11000B) is finally obtained.
This is why it is called a ripple adder, as at each stage the carry out of the previous block is fed in, after a delay into the next block, and so the carry “ripples” from the first to the last block of the ripple adder, in stages/iterations.
These carries are stored as temporary values in the code and so are not included in the waveforms produced. 3. Modify the test bench code to include the value of the carry-in (ci) to be a logic ‘1’ after 10ns.
This task was accomplished by adding the command
“ci 1001B +
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