1.Translate the following high level code into MIPS Assembly code. High Level code int main() { ... int y; y = divideNumbers (9, 3); ... } int divideNumbers (int a, int b) { int i; int result = 0; for (i=a; i>0; i = i-b) { result = result + 1; } return result; } 2.How many instructions are executed to run the above program?

1.Translate the following high level code into MIPS Assembly code. High Level code int main() { ... int y; y = divideNumbers (9, 3); ... } int divideNumbers (int a, int b) { int i; int result = 0; for (i=a; i>0; i = i-b) { result = result + 1; } return result; } 2.How many instructions are executed to run the above program?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ C
It is feasible for compilers and assemblers to be built to sequence assembly language instructions in a pipeline in a way that poses the fewest dangers. To achieve optimal efficiency, do all assemblers and compilers rearrange assembly language instructions in the same way?
A computer architecture simulator is a program that simulates the execution of computer architecture. Run the simulator with the following MIPS assembly program .data array: .word 1, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37 sum: .word 0 # this location will contain the sum .text .globl main main: la $s0, array li $t1, 12 add $t2, $zero, $zero loop: addi $t1, $t1, -1 sll $t3, $t1, 2 add $t3, $s0, $t3 lw $t0, 0($t3) add $t2, $t2, $t0 bne $t1, $zero, loop exit: la $s0, sum sw $t2, 0($s0) Write a report to describe the assembly program with a comment for each instructor, the comment need to describe the instruction types (data movement, data manipulation, control, etc.), address mode used (direct, indirect, register direct, register indirect, displacement, immediate) and the role for each register used. Also attach a set of full screen shots with time stamps to show the simulations characteristics and results.
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Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?