Address of Contents of Cache Blocks After Reference Memory Evicted Block Accessed Hit or Miss Block Set o Set 0 Set 1 Set 1 Miss Mem[0] 1 Miss Mem[0] Mem[1) Miss Mem[0] Mem[2) Mem[1] 3 Miss Mem[0] Mem[2] Mem[1] Mem[3] 4 Miss Mem[4] Mem[2] Mem[1] Mem[3] ...
In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.”
Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 16, 0
Assuming an LRU replacement policy, how many hits does this address sequence exhibit?
Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit?
Simulate a random replacement policy by flipping a coin. For example, “heads” means to evict the fi rst block in a set and “tails” means to evict the second block in a set. How many hits does this address sequence exhibit?
Which address should be evicted at each replacement to maximize the number of hits? How many hits does this address sequence exhibit if you follow this “optimal” policy?
Describe why it is diffi cult to implement a cache replacement policy that is optimal for all address sequences.
Assume you could make a decision upon each memory reference whether or not you want the requested address to be cached. What impact could this have on miss rate?
![Address of
Contents of Cache Blocks After Reference
Memory
Evicted
Block Accessed
Hit or Miss
Block
Set o
Set 0
Set 1
Set 1
Miss
Mem[0]
1
Miss
Mem[0]
Mem[1)
Miss
Mem[0]
Mem[2)
Mem[1]
3
Miss
Mem[0]
Mem[2]
Mem[1]
Mem[3]
4
Miss
Mem[4]
Mem[2]
Mem[1]
Mem[3]
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