Assume that we compile a program with two different compilers for the same ISA, then run the two executables on the same machine M. Version A has a dynamic instruction count of 2.0 x 109 and an execution time of 4 seconds, while version B has a dynamic instruction count of 2.5 x 109 and an execution time of 6 seconds. (a). Find the CPIs for the two executables (Version A and Version B) respectively given that machine M has a frequency of 2GHz (i.e. 2x109 Hz). (b). We further run the two executables on two different processors of the same ISA. Suppose the execution times on the two processors are the same. Using the CPIs from (a), compare the clock of the processor running Version A against the clock of the processor running Version B. Which clock is faster? By how much?

Assume that we compile a program with two different compilers for the same ISA, then run the two executables on the same machine M. Version A has a dynamic instruction count of 2.0 x 109 and an execution time of 4 seconds, while version B has a dynamic instruction count of 2.5 x 109 and an execution time of 6 seconds. (a). Find the CPIs for the two executables (Version A and Version B) respectively given that machine M has a frequency of 2GHz (i.e. 2x109 Hz). (b). We further run the two executables on two different processors of the same ISA. Suppose the execution times on the two processors are the same. Using the CPIs from (a), compare the clock of the processor running Version A against the clock of the processor running Version B. Which clock is faster? By how much?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining independent parts (A, B or C) can run in parallel?
2. Suppose we have two implementations of the same instruction set architecture.Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some programand computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the sameprogram. Which computer is faster for this program and by how much?
Compare compilers A and B for a program, where compiler A results in a dynamic instruction count of 6.9x10^9 and an execution time of 5 seconds, and compiler B results in a dynamic instruction count of 5.1x10^9 and an execution time of 4 seconds. a. Find the average CPI for each program, given a processor clock cycle time of 2 ns. b. If the compiled programs run on two different processors with the same execution times, what is the relative speed of the processor clocks?
Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz. Computer B has a CPI of 2.5 and can be run at a clock rate of 750 MHz. We have a particular program we wish to run. When compiled for computer A, this program has exactly 100,000 instructions. How many instructions would the program need to have when compiled for Computer B, in order for the two computers to have exactly the same execution time for this program? Please explain how to solve
Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz.Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. Wehave a particular program we wish to run. When compiled for computer A, thisprogram has exactly 100,000 instructions. How many instructions would theprogram need to have when compiled for Computer B, in order for the twocomputers to have exactly the same execution time for this program?
Consider two different implementations of the same instruction set architecture. The instructions can be divided into three classes according to their CPI (class A, B, C). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, and 3, and P2 with a clock rate of 3 GHz and CPIs of 2, 2, 2. Given a program with a dynamic instruction count of 1.0E6 instructions divided into classes as follows: 30% class A, 30% class B, 40% class C, which implementation is faster? What is the global CPI for each implementation? Find the clock cycles required in both cases.
Suppose that the execution time of a given program on a single processor is 9.5 ms. If you run this program on a system having 18 independent processors, you observe an overall speedup of 1.1. Using Amdahl’s Law, what must have been the fraction of the program that could be executed in parallel? (Express the answer in decimal form, i.e., if 50% of the program can be enhanced, enter 0.5. Round to three decimal places)
Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
It is feasible to set up a compiler for assembly language and an assembler in such a way that a pipeline is exposed to the least amount of danger imaginable. One of the goals of pipeline design is to do this. To reach the highest possible level of productivity, do all assemblers and compilers rearrange the instructions that are delivered in assembly language in the same way?
Both symmetric and asymmetric approaches to multiprocessing are possible. What are the benefits of using several processors in a single programme, as well as the drawbacks of doing so?
Consider two different implementations, P1 and P2, of the same instruction setarchitecture. There are four classes of instructions (A, B, C, and D).P1 has a clock rate of 1.5 GHz and CPI for each instruction class is as follows:Class CPI for this classA 1B 2C 3D 4P2 has a clock rate of 2.0 GHz and CPI for each instruction class is as follows:Class CPI for this classA 2B 2C 2D 2a. Given a program with 106 instructions divided into classes as follows: 10% classA, 20% class B, 50% class C and 20% class D, which implementation is faster?