I need the answer as soon as possible Consider a cache memory having the hit ratiosfor read and write operations are 70% and 80%respectively. Cache memory access time is100ns and main memory access time is 800ns.When miss occurs then 4 word block is copiedfrom the main memory to cache memory. CPUgenerates 60% write requests and remaining areused for read operations. What is the throughput(or) bandwidth of the cache in terms of millionwords/sec using Write back policy?

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Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Suppose that a computer has a processor with two L1 caches, one for instructions and one for data, and an L2 cache. Let τ be the access time for the two L1 caches. Themiss penalties are approximately 15τ for transferring a block from L2 to L1, and 100τ fortransferring a block from the main memory to L2. For the purpose of this problem, assumethat the hit rates are the same for instructions and data and that the hit rates in the L1 andL2 caches are 0.96 and 0.80, respectively.(a) What fraction of accesses miss in both the L1 and L2 caches, thus requiring accessto the main memory?(b) What is the average access time as seen by the processor?(c) Consider the following change to the memory hierarchy. The L2 cache is removedand the size of the L1 caches is increased so that their miss rate is cut in half. Whatis the average memory access time as seen by the processor in this case
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Consider a two-tier memory system consisting of cache (SRAM) and main memory (DRAM). The cache access time is 1 nsec and the main memory access time is 50 nsecs. (1 nsec = 1 ́ 10-9 secs). (a) What is the overall memory access time given a cache hit rate of 95%? (b) What will the cache hit rate need to be if the overall memory access time in (a) is to be halved?
Consider a cache with the following parameters: N (associativity) = 2, b (block size) = 2 words, W (word size) = 32 bits,C (cache size) = 32 K words, A (address size) = 32 bits. You need consider only word addresses.(a) Show the tag, set, block offset, and byte offset bits of the address. State how many bits are needed for each field.(b) What is the size of all the cache tags in bits?(c) Suppose each cache block also has a valid bit (V) and a dirty bit (D). What is the size of each cache set, including data, tag, and status bits?(d) Design the cache using the building blocks in Figure 8.28 and a small number of two-input logic gates. The cache design must include tag storage, data storage, address comparison, data output selection, and any other parts you feel are relevant. Note that the multiplexer and comparator blocks may be any size (n or p bits wide, respectively), but the SRAM blocks must be 16K × 4 bits. Be sure to include a neatly labeled block diagram. You need only design the…
Q3 If a microprocessor has L1 and L2 caches. The access time for L1 cache is τ. The miss penalties for transferring a block of memory from L2 to L1 is 10τ and it takes 120τ for transferring a block from memory to L2. The hit rates are the same for instructions and data and that the hit rates in the L1 and L2 caches are 0.90 and 0.85, repectively. I. Determine the fraction of accesses miss in both the L1 and L2 caches, thus requiring access to the main memory? II. What is the average access time as seen by the processor? Q4 Determine the number of bytes included in the address ranging from 123000H to 0C37000H, you must present the answers using units of Mbytes, Kbytes and bytes. Q5 If the size of a program is 424892 Bytes and its starting address is 000000H, determine the ending address of the program.
6. If a cache access requires one clock cycle and dealing with cache misses requires an additional five clock cycles, which of the following cache hit rates results in an effective access time of 2 clock cycles? Assume that the cache is using the sequential access. Group of answer choices 0.85 0.8 0.7 0.9
Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 13 bits wide.The cache is 4-way set associative (E = 4), with a 4-byte block size(B = 4) and eight sets (S = 8).Consider the following cache state. All addresses, tags, and valuesare given in hexadecimal format. The Index column contains the set index for each set of four lines. The Tag columns contain the tag value for each line. The V columns contain the valid bit for each line. The Bytes 0−3 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size (C) of this cache in bytes?B. The box that follows shows the format of an address (1 bit perbox). Indicate (by labeling the diagram) the fields that would beused to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tag
For a system, RAM = 64KB, Block size = 4 bytes, Cache size = 128 bytes, Direct mapped cache.Calculate the Hit ratio while CPU runs program “Test_Cache”. Also count how many blocks arereplaced in cache memory assuming the cache is empty at the beginning.For the same RAM, block size and Cache memory, what would be the Hit ration in case of FullyAssociative Mapping?For the same RAM, block size and Cache memory, what would be the Hit ration in case of 4-way SetAssociative Mapping?Main Program—“Test_Cache”