For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache: Tag Index Offset 31-10 9-6 5-0 1. What is the cache block size (in words)? 2. How many entries does the cache have?  3. What is the ratio between total bits required for such a cache implementation over the data storage bits

Computer Networking: A Top-Down Approach (7th Edition)
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Chapter1: Computer Networks And The Internet
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For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache:

Tag Index Offset
31-10 9-6 5-0

1. What is the cache block size (in words)?

2. How many entries does the cache have? 

3. What is the ratio between total bits required for such a cache implementation over the data storage bits? 

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