For the standard TTL gate circuit below, in HIGH state, the input current for any gate is 40 µA and the output current is 400 µA. In LOW state the input current is 1.6 mA and the output current is 16 mA. Are any of the gates in figure below overloaded? If so, which ones?

For the standard TTL gate circuit below, in HIGH state, the input current for any gate is 40 µA and the output current is 400 µA. In LOW state the input current is 1.6 mA and the output current is 16 mA. Are any of the gates in figure below overloaded? If so, which ones?

Electric Motor Control

10th Edition

ISBN:9781133702818

Author:Herman

Publisher:Herman

Chapter22: Sequence Control

Section: Chapter Questions

Problem 6SQ: Draw a symbol for a solid-state logic element AND.

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KVL and KCL

KVL stands for Kirchhoff voltage law. KVL states that the total voltage drops around the loop in any closed electric circuit is equal to the sum of total voltage drop in the same closed loop.

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For the standard TTL gate circuit below, in HIGH state, the input current for any gate is 40
µA and the output current is 400 µA. In LOW state the input current is 1.6 mA and the
output current is 16 mA. Are any of the gates in figure below overloaded? If so, which ones?
G

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