he smallest addressable unit in memory is an 8-bit byte B. Assume that first quarter of the address space (starts at the address 0x00000) is dedicated to HYP23’s RAM memory and the upper half of the address space is reserved for HYP23’s Flash memory. Give address ranges for the RAM and Flash memories. Fill in the table below. What are the sizes of the RAM memory and the Flash memory? Start Byte Address End Byte Address RAM memory Flash memory RAM memory size [Bytes/KiB]:____________________________ Flash memory size [bytes/KiB]:_______

he smallest addressable unit in memory is an 8-bit byte B. Assume that first quarter of the address space (starts at the address 0x00000) is dedicated to HYP23’s RAM memory and the upper half of the address space is reserved for HYP23’s Flash memory. Give address ranges for the RAM and Flash memories. Fill in the table below. What are the sizes of the RAM memory and the Flash memory? Start Byte Address End Byte Address RAM memory Flash memory RAM memory size [Bytes/KiB]:______________________ Flash memory size [bytes/KiB]:_

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
Consider a hypothetical microprocessor generating a 16-bit address (e.g., assume the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”? What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory”? What architectural features will allow this microprocessor to access a separate “I/O space”? If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain.
Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16-bits wide) and having a 16-bit data bus. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”? What is the maximum memory address space that the processor can access directly if it connected to an “8-bit memory”? What architectural features will allow this microprocessor to access a separate I/O spece? If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports can the microprocessor support? Are the values in d and e the same?
consider a processor using 32-bit memory addresses, also a 4 KiB (of actual data) direct-mapped cache memory that stores 32 bits of data for each address. The number of index bits is?
Suppose a byte-addressable computer using 4-way setassociative cache has 216 words of main memory (where each word is 32 bits) and a cache of 32 blocks, where each block is four words. Show the main memory address format for this machine. (Hint: Because this architecture is byte addressable, and the number of addresses is critical in determining the address format, you must convert everything to bytes.)
Consider a memory implemented for 8086 microprocessor Draw the memory block diagram. Determine the values for A0 , /BHE ,address lines(A1..A19) and data lines(D0.. D15) in order to access: A byte at odd address [01FF3H] A byte at even address [01FFCH] A word at even address [01FFEH] A word at odd address [01ABFH]
Consider a memory-management system based on paging. The total size of the physical address space 64 MB, Pages of size 4 KB, the Logical address space of 4GB. total number of pages are 16384, total number of frames are 16384 and the number of entries in a page table are 1048576.Now Calculate: a)Size of Page Table b) No of bits in Physical Address c) No of Bits in Logical Address
Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of 6 addressingmodes, and it has 60 computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.
Consider a hypothetical microprocessor having 32-bit instructions composed of two fields: the first Byte contains the opcode and the remainder the immediate operand or operand address. What is the maximum directly accessible memory capacity (in Bytes)? Discuss the impact on the system speed if the microprocessor bus has: a 32-bit local address bus and a 16-bit local data bus a 16-bit local address bus and a 16-bit local data bus
Consider a processor that uses a 48-bit virtual memory address. The main memory installed onthe system is 4GB. Page size is set to be 32KB. Determine the following:I. Address space of virtual memory and physical memory. II. Total Number of virtual pages and the total physical pagesIII. How many bits are necessary to store (i) Page Table entry and (ii) TLB entry, consideringthe TLB entry stores valid, reference and dirty bits.IV. What is the size of the page table? And how many pages of memory is needed to storethe entire Page table? What fraction of physical memory is needed to store the entirepage table?
Unlike a byte that is always 8 bits, word size can vary from machine to machine. Let's say we have a 16-bit system (word size is 2 bytes) and a memory unit that has 10 address lines. Because there are 10 address bits, we can have 210 unique addresses, hence 1024 addresses. If we are working with something word-addressable, that means each word has a unique address, and we canstore 1024 words. The memory size is 1 kiloword, or equivalently, 2kilobytes because each word is 2 bytes long. The address of the first word is 0, the second word is 1, the third word is 2, and the last word is 1023.Now, with 4 address lines and a word size of 4 bits, what is the address of the last word?
Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining independent parts (A, B or C) can run in parallel?