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In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.” Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0. 1. Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.  2. Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.

In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.” Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0. 1. Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.  2. Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence “0, 1, 2, 3, 4.”

Consider the following address sequence: 0, 2, 4, 8, 10, 12, 14, 8, 0.

1. Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed. 

2. Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Please show the status of the cache after each address is accessed.

Address of Contents of Cache Blocks After Reference Memory Evicted Block Accessed Hit or Miss Block Set 0 Set o Set 1 Set 1 Miss Mem[0] 1. Miss Mem[0] Mem[1] 2 Mem[2] Mem[1] Miss Mem[0] Mem(0] Mem[4] 3 Miss Mem[2] Mem[1] Mem[3] 4 Miss Mem[2] Mem[1) Mem[3] ..
Transcribed Image Text:Address of Contents of Cache Blocks After Reference Memory Evicted Block Accessed Hit or Miss Block Set 0 Set o Set 1 Set 1 Miss Mem[0] 1. Miss Mem[0] Mem[1] 2 Mem[2] Mem[1] Miss Mem[0] Mem(0] Mem[4] 3 Miss Mem[2] Mem[1] Mem[3] 4 Miss Mem[2] Mem[1) Mem[3] ..
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