Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 ps Q1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?

Suppose we had a processor design with 5 stages where each stage takes the following amount of time: IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 ps Q1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions such that the brief ramp up period at the beginning and the ramp down period at the end with less than 100% utilization does not matter. Q2: If you choose a pipelined design, what is the average execution time per instruction in picoseconds?

Name: Suppose we had a processor design with 5 stages where each stage takes
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Description: Suppose we had a processor design with 5 stages where each stage takes the following amount of time:IF: 400 ps ID: 200 ps EX: 300 ps MEM: 500 ps WB: 200 psQ1: If you choose a pipelined design, what is the CPI? Assume that we have enough instructions

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?
Suppose on a non-pipelined single-processor machine, you have the following breakdown: alu instructions make up 25% of the dynamic instruction count, and take 2 cycles to execute. Load/store instructions take 10 cycles to execute and make up 30% of the mix. Jumps take 4 cycles and make up 15%. All other instructions average 1.5 cycles. a. What is the average CPI? b. Suppose the architecture above is pipelined. If there are no stalls for any reason, what is the new CPI? c. If, for the architecture described in questions a and b, Load/store instructions generate 2 stalls on average, alu 0.2 stalls, and jumps cause 1 stall, what is the actual pipelined cpi?
Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?
ANSWER THE QUSTIONS THAT IS WRITEN OR ON THE PICTURE PLEASE Question 6: Suppose in a program there are 120 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the speedup of pipeline parallel processing. Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing. Question 8: Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.
If a non-pipelined processor had a maximum clock rate of 500 MHz and was converted to a perfectly balanced 10-stage pipeline, what would the pipelined processor's maximum clock rate be? A. 500 nanoseconds B. 500 picoseconds C. 500 GHz D. 50 GHz E. 5 GHz
consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the Section I B of "Advanced Systems Concepts", i.e.:  a one clock cycle fetch  a two clock cycle decode  a three clock cycle execute and a 200 instruction sequence: Show your work. 7. o pipelining would require _____ clock cycles: 8. A scalar pipeline would require _____ clock cycles: How high is the increase in speed (percentage) compared to no pipelining? 9. A superscalar pipeline with two parallel units would require ______ clock cycles: How high is the increase in speed (percentage) compared to no pipelining?
Describe pipelining in terms of boosting the performance of the processor, and then compute the number of cycles that will be required to execute five instructions assuming that each portion of the machine requires one cycle. a. Without using pipelines; b. By using pipelines a. With pipelined processes b. With pipelined processes c. With pipelined processes d. With pipelined processes d.
Pipeline performance. Suppose processor A executes instructions in the following 4 stages (no pipeline), where each stage could run this fast. Compare the performance of a pipelined vs. unpipelined implementation of processor A.IF&ID | 25nsEX | 20nsMem | 40nsWB | 15nsDraw the pipeline diagram to show clock cycles with time. Compare the performance of a pipelined vs. unpipelined implementation of processor A.
A hypothetical processor has 9 stages of a pipeline as shown in the table below. The first row in the table below shows the pipeline stage number, second row gives the name of each stage, and third row gives the delay of each stage in Nano-seconds. The name of each stage describes the task performed by it. Each stage takes 1 cycle to execute. This processor stores all the register contents in a compressed fashion. After fetching the operands the operands are first decompressed, and before saving the results in register file, the results are first compressed. a)How many cycles are required to execute one instruction on this pipeline? b)How many cycles are required to execute 19 instructions on this pipeline? Assume that no stall cycles occur during the execution of all instructions. c) Assume that all necessary bypass/forwarding circuitry is implemented in this 9 stage pipeline. How many cycles will the pipeline stall during the execution of below given two instructions? Briefly explain…
Q: Consider three different processors P1, P2, and P3 that support the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. (a) Which processor has the highest performance expressed in instructions per second? Show your calculations. (b) If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions for each processor. (c) We are trying to reduce the execution time by 30% (i.e., execution time is reduced from 10 seconds to 7 seconds). However, this leads to an increase of 20% in the CPI. For each processor, what clock rate should we have to get this time reduction? (Show the calculations you did to answer this question.)
Task 1 | You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. If the 5 stages are Ins, 1.5ns, 4ns, 3ns, and 0.5ns and the pipeline stalls 20% of the time for 1 cycle and 5% of the time for 2 cycles (these occurrences are disjoint). What is the speedup compared to the original processor? (Assume average CPI for a pipelined processor is Iand each pipeline stage added also adds 20ps due to register setup delay, Evaluate the answer upto two decimal places) Be quick and accurate
Suppose without pipelining, a processor takes 100sec to complete execution of 05 instructions, assuming each instruction require same amount of time for execution. If we can have 5 stage ideal pipeline for the same processor, then How much time will it take to complete execution of these 05 instructions? How much speedup we can achieve?