SET reg, immed ; 3 clock cycles LOAD reg, mem ;4 clock cycles ADD reg, reg ; 3 clock cycles ADD reg, immed ; 2 clock cycles LOOP _LabelName ; 8 clock cycles Assume that the following code fragment is used to sum the element of a numeric arn SET reg1, 0 SET reg2, MAX_SIZE ;initialize loop counter SET reg3, @list ;initialize array pointer ProcessArray: LOAD reg4, [reg3] ;fetch current list element ;initialize sum ADD ro1 road add current list olement
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- _____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.Most Intel CPUs use the __________, in which each memory address is represented by two integers.A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.
- Suppose that a RISC machine uses five register windows.Q) How deep can the procedure calls go before registers must be saved in memory? (That is, what is the maximum number of “active” procedure calls that can be made before we need to save any registers in memory?Consider a memory implemented for 8086 microprocessor Draw the memory block diagram. Determine the values for A0 , /BHE ,address lines(A1..A19) and data lines(D0.. D15) in order to access: A byte at odd address [01FF3H] A byte at even address [01FFCH] A word at even address [01FFEH] A word at odd address [01ABFH]Interface an 80286 microprocessor with total memory size 128KB using RAM chip size of 16KB. Show the detail of your drawing.
- Suppose you have a computer that does instruction processing in anatomic way, with a clock cycle of 7ns and one instruction executioncompleted every cycle.You now split the processing into the five stages of the RISC pipeline,and you get required processing times of• IF: 1ns• ID: 1.5ns• EX: 1ns• MEM: 2ns• WB: 1.5nsYou now have added 0.1ns of delay between each of these stages. What’s the clock cycle time of this 5-stage pipelined machine?Suppose an instruction takes four cycles to execute in a nonpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a four-stage pipeline, that instruction still takes four cycles to execute, so how can we say the pipeline speeds up the execution of the program?Suppose we have a 32-bit RISC-V word containing the value 0x00A12423. We would like to know what RISC-V machine instruction this represents. Translate this instruction to assembly language. Use symbolic register names like t0 instead of absolute register numbers like x5.
- Suppose a RISC machine uses overlapping register windows for passing parameters between procedures. The machine has 298 registers. Each register window has 32 registers, of which 10 are global variables and 10 are local variables.Q) By how much would the current window pointer (CWP) be incremented at each procedure call?Suppose a RISC machine uses overlapping register windows for passing parameters between procedures. The machine has 298 registers. Each register window has 32 registers, of which 10 are global variables and 10 are local variables.Q) How many registers would be available for use by output parameters?In a computer instruction format, the instruction length is 16 bits, and the size of an address field is 4 Is it possible to have: 15 instructions with 3 addresses, 14 instructions with 2 addresses, 31 instructions with one address, and 16 instructions with zero addresses, using this format? Justify your answer.