Microelectronics: Circuit Analysis and Design
Microelectronics: Circuit Analysis and Design
4th Edition
ISBN: 9780073380643
Author: Donald A. Neamen
Publisher: McGraw-Hill Companies, The
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Chapter 16, Problem 16.33P

(a)

To determine

The value of the input switching voltage and the input voltage for the given vO

(a)

Expert Solution
Check Mark

Answer to Problem 16.33P

The value of the input switching voltage is 1.7069V , input voltage for the output of 3.1V is 1.26V and the value of the input voltage for the output voltage of 0.2V is 2.157V .

Explanation of Solution

Calculation:

The given diagram is shown in Figure 1

  Microelectronics: Circuit Analysis and Design, Chapter 16, Problem 16.33P

The expression to determine the trans-conductance parameter for NMOS is given by,

  Kn=( k n2)(WL)n

Substitute 4 for (WL)n and 100μA/V2 for kn in the above equation.

  Kn=( 100 μA/ V 2 2)4=200μA/V2

The expression to determine the trans-conductance parameter for PMOS is given by,

  Kp=( k p2)(WL)p

Substitute 12 for (WL)p and 40μA/V2 for kp in the above equation.

  Kp=( 40 μA/ V 2 2)12=240μA/V2

The expression to determine the transition points VIt is given by,

  VIt=VDD+VTP+ k n k p VTN1+ k n k p VTN

Substitute 3.3V for VDD , 0.4V for VTP , 200μA/V2 for kn and 240μA/V2 for kp and 0.4V for VTN in the above equation.

  VIt=3.3V+( 0.4V)+ 240 μA/ V 2 200 μA/ V 2 ( 0.4V)1+ 240 μA/ V 2 200 μA/ V 2 ( 0.4V)=1.7069V

The expression to determine the value of the input voltage is given by,

  Kn(vIV TN)2=Kp[2( V DD v I+ V TP)( V DD v O )2( V DD v O)]2

Substitute 240μA/V2 for Kp , 200μA/V2 for Kn , 3.1V for vO , 0.4V for VTN , 3.3V for VDD and 0.4V for VTP in the above equation.

  [200μA/V2( v I 0.4V)2=[240μA/ V 2[ 2( 3.3V v I 0.4V ) ( 3.3V3.1V ) ( 3.3V3.1V ) 2 ]]]5vI21.6vI5.92=0vI=1.6± ( 1.6 ) 2 +4( 5.92 )( 5 )2(5)vI=1.26V

The expression to determine the value of the input voltage when the output voltage is more than 1.25V is given by,

  KnKp[2(vIVTN)vOvO2]=[VDDvI+( V TP)]2

Substitute 240μA/V2 for Kp , 200μA/V2 for Kn , 0.2V for vO , 0.4V for VTN and 3.3V for VDD in equation (1).

  200μA/ V 2240μA/ V 2[2( v i0.4V)0.2V( 0.2V)2]=[3.3VvI+( 0.4V)]26vI236.8vI+51.46=0vI=2.157V

Conclusion:

Therefore, the value of the input switching voltage is 1.7069V , input voltage for the output of 3.1V is 1.26V and the value of the input voltage for the output voltage of 0.2V is 2.157V .

(b)

To determine

The value of the input switching voltage and the input voltage for the given vO

(b)

Expert Solution
Check Mark

Answer to Problem 16.33P

The value of the input switching voltage is 1.2513V , input voltage for the output of 3.1V is 0.8554V and the value of the input voltage for the output voltage of 0.2V is 1.61V .

Explanation of Solution

Calculation:

The expression to determine the trans-conductance parameter for NMOS is given by,

  Kn=( k n2)(WL)n

Substitute 6 for (WL)n and 100μA/V2 for kn in the above equation.

  Kn=( 100 μA/ V 2 2)6=300μA/V2

The expression to determine the trans-conductance parameter for PMOS is given by,

  Kp=( k p2)(WL)p

Substitute 4 for (WL)p and 40μA/V2 for kp in the above equation.

  Kp=( 40 μA/ V 2 2)4=80μA/V2

The expression to determine the transition points VIt is given by,

  VIt=VDD+VTP+ k n k p VTN1+ k n k p VTN

Substitute 3.3V for VDD , 0.4V for VTP , 300μA/V2 for kn and 80μA/V2 for kp and 0.4V for VTN in the above equation.

  VIt=3.3V+( 0.4V)+ 300 μA/ V 2 80 μA/ V 2 ( 0.4V)1+ 300 μA/ V 2 80 μA/ V 2 ( 0.4V)=1.2513V

The expression to determine the value of the input voltage is given by,

  Kn(vIV TN)2=Kp[2( V DD v I+ V TP)( v DD v O )2( v DD v O)]2

Substitute 240μA/V2 for Kp , 200μA/V2 for Kn , 3.1V for vO , 0.4V for VTN , 3.3V for VDD and 0.4V for VTP in the above equation.

  200μA/V2( v I0.4V)2=[240μA/V2[ 2( 3.3V v I 0.4V ) ( 3.33.1V ) ( 3.33.1V ) 2 ]]15vI210.4vI2.08=0vI=0.8554V

The expression to determine the value of the input voltage when the output voltage is more than 1.25V is given by,

  KnKp[2(vIVTN)vOvO2]=[VDDvI+( V TP)]2

Substitute 240μA/V2 for Kp , 300μA/V2 for Kn , 0.2V for vO , 0.4V for VTN and 3.3V for VDD in equation (1).

  300μA/ V 280μA/ V 2[2( v i0.4V)0.2V( 0.2V)2]=[3.3VvI+( 0.4V)]24vI229.2vI+36.64=0vI=1.61V

Conclusion:

Therefore, the value of the input switching voltage is 1.2513V , input voltage for the output of 3.1V is 0.8554V and the value of the input voltage for the output voltage of 0.2V is 1.61V .

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Chapter 16 Solutions

Microelectronics: Circuit Analysis and Design

Ch. 16 - Consider the NMOS logic circuit in Figure 16.18....Ch. 16 - Repeat Exercise TYU 16.5 for the NMOS logic...Ch. 16 - The CMOS inverter in Figure 16.21 is biased at...Ch. 16 - swA CMOS inverter is biased at VDD=3V . The...Ch. 16 - A CMOS inverter is biased at VDD=1.8V . The...Ch. 16 - Prob. 16.7TYUCh. 16 - Repeat Exercise Ex 16.9 for a CMOS inverter biased...Ch. 16 - Determine the transistor sizes of a 3input CMOS...Ch. 16 - Design the widthtolength ratios of the transistors...Ch. 16 - Design a static CMOS logic circuit that implements...Ch. 16 - Prob. 16.10TYUCh. 16 - Prob. 16.11TYUCh. 16 - Sketch a clocked CMOS logic circuit that realizes...Ch. 16 - Prob. 16.12EPCh. 16 - Prob. 16.13TYUCh. 16 - Consider the CMOS transmission gate in Figure...Ch. 16 - Prob. 16.15TYUCh. 16 - Prob. 16.14EPCh. 16 - Prob. 16.16TYUCh. 16 - Prob. 16.17TYUCh. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Sketch an NMOS threeinput NOR logic gate. Describe...Ch. 16 - Discuss how more sophisticated (compared to the...Ch. 16 - Sketch the quasistatic voltage transfer...Ch. 16 - Discuss the parameters that affect the switching...Ch. 16 - Prob. 6RQCh. 16 - Sketch a CMOS threeinput NAND logic gate. Describe...Ch. 16 - sDiscuss how more sophisticated (compared to the...Ch. 16 - Prob. 9RQCh. 16 - Sketch an NMOS transmission gate and describe its...Ch. 16 - Sketch a CMOS transmission gate and describe its...Ch. 16 - Discuss what is meant by pass transistor logic.Ch. 16 - Prob. 13RQCh. 16 - Prob. 14RQCh. 16 - Prob. 15RQCh. 16 - Describe the basic architecture of a semiconductor...Ch. 16 - ‘Sketch a CMOS SRAM cell and describe its...Ch. 16 - Prob. 18RQCh. 16 - Describe a maskprogrammed MOSFET ROM memory.Ch. 16 - Describe the basic operation of a floating gate...Ch. 16 - Prob. 16.1PCh. 16 - Prob. 16.2PCh. 16 - (a) Redesign the resistive load inverter in Figure...Ch. 16 - Prob. D16.4PCh. 16 - Prob. 16.5PCh. 16 - Prob. D16.6PCh. 16 - Prob. 16.7PCh. 16 - Prob. 16.8PCh. 16 - For the depletion load inverter shown in Figure...Ch. 16 - Prob. 16.10PCh. 16 - Prob. D16.11PCh. 16 - Prob. D16.12PCh. 16 - Prob. 16.13PCh. 16 - For the two inverters in Figure P16.14, assume...Ch. 16 - Prob. 16.15PCh. 16 - Prob. 16.16PCh. 16 - Prob. 16.17PCh. 16 - Prob. 16.18PCh. 16 - Prob. D16.19PCh. 16 - Prob. 16.20PCh. 16 - Prob. 16.21PCh. 16 - Prob. 16.22PCh. 16 - In the NMOS circuit in Figure P16.23, the...Ch. 16 - Prob. 16.24PCh. 16 - Prob. 16.25PCh. 16 - Prob. 16.26PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. D16.28PCh. 16 - Prob. D16.29PCh. 16 - Prob. 16.31PCh. 16 - Prob. 16.32PCh. 16 - Prob. 16.33PCh. 16 - Consider the CMOS inverter pair in Figure P16.34....Ch. 16 - Prob. 16.35PCh. 16 - Prob. 16.36PCh. 16 - Prob. 16.37PCh. 16 - Prob. 16.38PCh. 16 - Prob. 16.39PCh. 16 - (a) A CMOS digital logic circuit contains the...Ch. 16 - Prob. 16.41PCh. 16 - Prob. 16.42PCh. 16 - Prob. 16.43PCh. 16 - Prob. 16.44PCh. 16 - Prob. 16.45PCh. 16 - Prob. 16.46PCh. 16 - Prob. 16.47PCh. 16 - Prob. 16.48PCh. 16 - Prob. 16.49PCh. 16 - Prob. 16.50PCh. 16 - Prob. 16.51PCh. 16 - Prob. 16.52PCh. 16 - Prob. D16.53PCh. 16 - Figure P16.54 is a classic CMOS logic gate. (a)...Ch. 16 - Figure P16.55 is a classic CMOS logic gate. (a)...Ch. 16 - Consider the classic CMOS logic circuit in Figure...Ch. 16 - (a) Given inputs A,B,C,A,B and C , design a CMOS...Ch. 16 - (a) Given inputs A, B, C, D, and E, design a CMOS...Ch. 16 - (a) Determine the logic function performed by the...Ch. 16 - Prob. D16.60PCh. 16 - Prob. 16.61PCh. 16 - Prob. 16.62PCh. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Sketch a clocked CMOS domino logic circuit that...Ch. 16 - Prob. D16.65PCh. 16 - Prob. 16.66PCh. 16 - Prob. 16.67PCh. 16 - The NMOS transistors in the circuit shown in...Ch. 16 - Prob. 16.69PCh. 16 - Prob. 16.70PCh. 16 - Prob. 16.71PCh. 16 - (a) Design an NMOS pass transistor logic circuit...Ch. 16 - Prob. 16.73PCh. 16 - What is the logic function implemented by the...Ch. 16 - Prob. 16.75PCh. 16 - Prob. 16.76PCh. 16 - Prob. 16.77PCh. 16 - Consider the NMOS RS flipflop in Figure 16.63...Ch. 16 - Prob. 16.79PCh. 16 - Consider the circuit in Figure P16.80. Determine...Ch. 16 - Prob. D16.81PCh. 16 - Prob. 16.82PCh. 16 - Prob. 16.83PCh. 16 - Prob. 16.84PCh. 16 - (a) A 1 megabit memory is organized in a square...Ch. 16 - Prob. 16.86PCh. 16 - Prob. 16.87PCh. 16 - Prob. 16.88PCh. 16 - Prob. D16.89PCh. 16 - Prob. 16.90PCh. 16 - Prob. 16.91PCh. 16 - Prob. 16.92PCh. 16 - Prob. D16.93PCh. 16 - Prob. D16.94PCh. 16 - Prob. D16.95PCh. 16 - An analog signal in the range 0 to 5 V is to be...Ch. 16 - Prob. 16.97PCh. 16 - Prob. 16.98PCh. 16 - Prob. 16.99PCh. 16 - The weightedresistor D/A converter in Figure 16.90...Ch. 16 - The Nbit D/A converter with an R2R ladder network...Ch. 16 - Prob. 16.102PCh. 16 - Prob. 16.103PCh. 16 - Prob. 16.104PCh. 16 - Prob. 16.105PCh. 16 - Design a classic CMOS logic circuit that will...Ch. 16 - Prob. D16.111DPCh. 16 - Prob. D16.112DPCh. 16 - Prob. D16.113DP
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