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0010 001r 0011 0aaa 0011 laaa 0100 laaa 0101 0aaa 0111 raaa 1000 raaa 1001 raaa Rotate right r Decimal input trap Decimal output trap Character input Character output Add to r Subtract from r Bitwise AND to r ΝΑ d d, i d d, i d, i d, i d, i C NZV NZVC NZVC NZ

0010 001r 0011 0aaa 0011 laaa 0100 laaa 0101 0aaa 0111 raaa 1000 raaa 1001 raaa Rotate right r Decimal input trap Decimal output trap Character input Character output Add to r Subtract from r Bitwise AND to r ΝΑ d d, i d d, i d, i d, i d, i C NZV NZVC NZVC NZ

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Use the PEP/8 assembely machine language simulator to write a program that simulates the PEP/8 computer
and instruction set for only the following instructions (the following instructions are in the image attached)
Here are some specifics.
 
1.Use an array to represent the memory.
 
2.Use variables or arrays for the PEP8 registers. I recommend putting it all into a
structure. I also recommend using an array of 16 bit values for A, X, PC, SP so
that you can use the r bit from the instructions to point directly to A or X. You do NOT
have to include the Status bits.
Instruction Specifier 0000 0000 0001 100r 0001 110r 0001 111r 0010 000r 0010 001r 0011 0aaa 0011 laaa 0100 laaa 0101 0aaa 0111 raaa 1000 raaa 1001 raaa 1010 raaa 1100 raaa 1101 raaa 1110 raaa 1111 raaa Instruction Stop execution Bitwise invert r Arithmetic shift left r Arithmetic shift right r Rotate left r Rotate right r Decimal input trap Decimal output trap Character input Character output Add to r Subtract from r Bitwise AND to r Bitwise OR to r Load r from memory Load byte from memory Store r to memory Store byte r to memory Addressing Modes ΝΑ ΝΑ ΝΑ ΝΑ ΝΑ ΝΑ d d, i d d, i d, i d, i d, i d, i d, i d, i d d Status Bits NZ NZVC NZC C C NZV NZVC NZVC NZ NZ NZ NZ
Transcribed Image Text:Instruction Specifier 0000 0000 0001 100r 0001 110r 0001 111r 0010 000r 0010 001r 0011 0aaa 0011 laaa 0100 laaa 0101 0aaa 0111 raaa 1000 raaa 1001 raaa 1010 raaa 1100 raaa 1101 raaa 1110 raaa 1111 raaa Instruction Stop execution Bitwise invert r Arithmetic shift left r Arithmetic shift right r Rotate left r Rotate right r Decimal input trap Decimal output trap Character input Character output Add to r Subtract from r Bitwise AND to r Bitwise OR to r Load r from memory Load byte from memory Store r to memory Store byte r to memory Addressing Modes ΝΑ ΝΑ ΝΑ ΝΑ ΝΑ ΝΑ d d, i d d, i d, i d, i d, i d, i d, i d, i d d Status Bits NZ NZVC NZC C C NZV NZVC NZVC NZ NZ NZ NZ
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