3.67 Given the circuit below, derive the output f(a, b, c, d) in minterm list form. Consider B to be the MSB for both the decoder and the multiplexer. Assume positive logic (active-high inputs and outputs). m0 m1 m2 m3 2-to-4 Decoder BA a b DO D1 D2 D3 4-to-1 MUX BA d Y f(a, b, c, d)
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- F(A,B,C,D) = (B'+D')(A+C'D)+BCD' 1. Find Minterms and Maxter, in short notation 2. Draw logic diagramLogic Gates:* 7404LS (NOT)* 7408LS (AND)* 7432LS (OR)* 7400LS (NAND)* 7402LS (NOR)* 7486LS (EX-OR)Or you can use 74HCxx versions.Task 1: 2-to-1 LINE MULTIPLEXER DESIGNA) Write the truth table of 2-to-1 line multiplexer.B) Draw the circuit diagram by using only NAND & NOT GATES.C) Simulate the circuit that you found in part B.Give the logic diagram of half subtractor. NOTE: SUB: DIGITAL LOGIC AND DESIGN(DLD) DEPTT:CS/IT.
- Draw the output waveform C and D, given the input waveforms A and B as shown belowfigure 2.Figure 2b) Verify the result from part (a) by any using simulation tools. (Screen shoot only for thefollowing input cases: when (A=0, B=0), (A=1, B=0) and (A=0, B=1). c) For the logic circuit given in Figure 3, obtain the output expression for ?Q (A, B, C) = A̅ .B̅. C +A̅ .B. C + A .B. C̅ + A.B.C Karnaugh function given in the form Using the mapping method, you can use the simplified function separately in terms of minterms and maxterms. obtain. Output functions with AND NOT for minterms and OR for maxters. Install separately with logic doors.Q (A, B, C) = A' .B'. C +A' .B. C + A.B.C' + A.B.C Obtain the simplified function with the Karnaugh Map method in terms of minterms and maxters separately. Set the output functions separately with logic gates with ANDNOT for minterms and ORNOT for maxterms.
- Q (A, B, C) = A̅ .B̅. C +A̅ .B. C + A .B. C̅ + A.B.C Karnaugh function given in the form Using the mapping method, you can use the simplified function separately in terms of minterms and maxters. obtain. Output functions with AND NOT for minterms and OR for maxters. Install separately with logic doors.From the following truth table: i) Construct Karnaugh Map (SOP)ii) Design combinational logic circuit using 2-input NAND Gateiii) Design combinational logic circuit using 4:1 MultiplexerGiven the function G=(A’+B+C)(A’+B’+C’)(A+B+C) Draw the logic circuit diagram ofthe simplified OR-AND form
- 1:The output of a logic gate is 1 when all the input are at logic 1 and a . OR and EX - NOR Gate b . AND Gate and EX - OR Gate C. OR and EX - OR Gate d . NAND and OR Gate 2: Choose an application of A / D convertor a. Sonar systems b. Radars and Jammers C. Digital Audio apllications d. Encoders 3: Find the simplification of AB + B ( B + C ) + C ( B + C ) a. C + A b. B + C c. 1 d. A + 4: Choose a correct number of input lines for a decoder which has 128 output lines a . 14 b . 7 c . 1 d . 128 6: Select a suitable example for sequential logic circuit . a . Encoder b . None of the given choices c . Counters d . PALDraw the logic diagram for the following functions, then map it using NAND only technology and NOR only technology: F = y’z + y(x + w) Y = A’B’ + B (A + C)+ C’D+ DUsing Logisim, draw the combinational logic circuit diagram by using the equation: (ab’ . (a + c))’ + a’b . (a +b’ + c’)’