Assume that the following RISC-V code is executed on a pipelined processor with a 5-stage pipeline with full forwarding and a predict-taken branch predictor. Draw the pipeline diagram and report number of clock cycles it takes to execute this sequence of instructions. Note: Result of branch is determined in EXE stage. Labell: Label2: 1w X1, 40 (X6) beq X2 add X1 beq x1 SW X2 and X1 I I I I I X3 Label2 X6 X4 X2 I 20 (X4) X1 X4 " " " Label1 * Please solve correctly. Thank you. #Not Taken #Not Taken

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