Assume the following sequence of instructions is executed on a five-stage pipelined datapath: add X11, X10, X5 ld X12, 8 (X11) 1d X13, 0 (X10) and X5, X10, X6 or X15, X13, XO add X6, X5, XO Assume that the register write is done in the first half of cycle and register read happens in the second half of cycle; draw the pipeline diagram for the following cases: a) If there is no forwarding or hazard detection, insert NOPs to ensure correct execution. b) Re-arrange the code to avoid NOPs. c) If forwarding is applied, show forwarding path using connections between stages. Please handwrite your answers and solve correctly. Thank you.

Assume the following sequence of instructions is executed on a five-stage pipelined datapath: add X11, X10, X5 ld X12, 8 (X11) 1d X13, 0 (X10) and X5, X10, X6 or X15, X13, XO add X6, X5, XO Assume that the register write is done in the first half of cycle and register read happens in the second half of cycle; draw the pipeline diagram for the following cases: a) If there is no forwarding or hazard detection, insert NOPs to ensure correct execution. b) Re-arrange the code to avoid NOPs. c) If forwarding is applied, show forwarding path using connections between stages. Please handwrite your answers and solve correctly. Thank you.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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