Cache Write Policies In a cache system using a write-back policy, if a cache block is modified and marked as "dirty" but not yet updated in the main memory, and that block is selected for replacement, what action should be taken to ensure data integrity?
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- Cache-unfulfilled requests from processors when a block is being written back to main memory from the write buffer are there any consequences?A message slot is a cache line that contains status flags and the message itself. The state can be empty or ready, and communication occurs through a single cache line. Both the sender and the receiver write the message to the cache line. The receiver updates the state from empty to ready, then polls the cache line in a loop waiting for the sender to send a message. The sender waits in a tight loop until the receiver acknowledges the cache line, changes the state from ready to empty, and acknowledges receipt. Explain that the system uses a snooping cache coherence protocol and describe the cache-coherence transaction taking place on the coherence bus when a message transfer occurs.“Prefetching” is a technique that leverages predictable address patterns to speculatively bring in additional cache blocks when a particular cache block is accessed. One example of prefetching is a stream buff er that prefetches sequentially adjacent cache blocks into a separate buff er when a particular cache block is brought in. If the data is found in the prefetch buff er, it is considered as a hit and moved into the cache and the next cache block is prefetched. Assume a two-entry stream buff er and assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block is completed. What is the miss rate for the address stream above?Cache block size (B) can aff ect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for various block sizes. 8: 4% 16: 3% 32: 2% 64: 1.5% 128: 1%…
- In the event of an unsatisfied cache request, what should happen to the block being sent to the main memory from the write buffer?Differentiate between caches that are totally associative and those that are directly mapped.When a block leaves the write buffer and returns to main memory, does anything need to happen if the processing unit makes a cache-unfulfilled request?
- A write through cache will always store any changes made in the cache in memory immediately replace the first item that was inserted into the cache when it is full use fully associative cache mapping set a dirty bit when the cache has been modified so the changes can be stored laterReplacement Policies Consider a cache using the Least Recently Used (LRU) policy with 16 blocks. If the sequence of memory block accesses is 3, 5, 2, 1, 5, 3, 4, 2, 1, what blocks will be present in the cache after these accesses?Cache Mapping Technique 1. Suppose a computer usingdirect-mapped cache has 2 bytes of byte=addressable main memory and a cache of32 blocks, where each cache block contains 16 bytes.a) How many blocksof main memory are there?b) What is theformat of a memory address as seen by the cache; that is, what are the sizes ofthe tag, block, and offset fields?c) To which cacheblock will the memory address 0x0DB63 map?2. Suppose a computer using fullyassociative cache has 2 bytes of byte-addressable main memory and a cache of128 blocks, where each cache block contains 64 bytes.a) How many blocksof main memory are there?b) What is theformat of a memory address as seen by the cache; that is, what are the sizes ofthe tag and offset fields?c) To which cacheblock will the memory address 0x01D872 map?3. A 2-way set-associative cacheconsists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressingis used.a) Show the mainmemory address format that allows us to map addresses from…
- Make a distinction between a cache that is entirely associative and a cache that is directly mapped.What is the role of a cache that is completely associative?3. The series of memory address references given as word addresses are 122, 126, 126, 126, 116, 300, 116, and 118. Assume a direct-mapped cache with eight one-word blocks that is initially empty. Label each reference in the list as a hit or miss and show the contents of the cache with figure after each reference.