Computer Organization The logical instructions above are not included in the MIPS instruction set, but are described above. If the value of $t2 = 0x00FFA5A5 and the value of $t3 = 0xFFFF003C, what is the result in $t1? (a and b)
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Computer Organization
The logical instructions above are not included in the MIPS
instruction set, but are described above. If the value of $t2 = 0x00FFA5A5 and the
value of $t3 = 0xFFFF003C, what is the result in $t1?
(a and b)
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- * H/W At a certain time, the simple computer registers contents the following data: PC = 1FFH, AR = B5CH, DR = 1234 H, AC = 6D97H, and IR = 08F5H. The memory contents at certain addresses are given below: (1) What is the instruction that will be fetched and executed? (2) instruction is executed. Show the binary operation that will be performed when the (3) end of the instruction cycle? Give the contents of the simple computer registers at the МЕMORY ADDRESS MEMORY DATA IN IN HEX. НЕХ. 1FF 7C48 B5C 5113 C48 A025 CD9 F517Let's assume %ecx = 0x000FFD0E and %eax= 0x000FED25 (Hexadecimal representation). What is the value in %ecx after the following instruction? orq %eax, %ecx Provide answer in hexadecimal representation. Acceptable answer format: 000003FD or 0x000003FDSP=1239H, SS=9876H, the physical address is AAAFOH Non of them 1BC06H 0AAAFH 99999H if BX=1000, DS=0400, and AL=EDH, for the following instruction: MOV [BX] + 1234H, AL. the physical address is 6324H O 4244H 4234H 6234H 6243H O
- if BX=1000, DS=0400, and AL=EDH, for the following instruction: MOV [BX] + 1234H, AL. the physical address is O 6243H O 4234H O 6234H O 6324H O 4244HB. For the following 8085 assemble code, calculate the total execution time 0100: LXI 0103: MVI C,0 0105: NOP 0106: NOP 0107: DER C D,1000H 0108: JNZ 0105H 010A: MOV A,M 010B: OUT 05H SKIP : C. what is the single instruction equivalent to the following code: XOR DX,DX TEST AX,8000H JZ NOT Total execution time = SKIP DXEvaluate the effect of the instruction LDR r5, [r7, #4], given the initial values below. Give the final values of all the registers. Registers: r5 = 100 r6 = 1000 r7 = 996 Memory Address Value 992 30 996 40 1000 50 1004 60 1008 70 O r5=50, r6=1000, r7=1000 O r5=40, r6=1000, r7=996 O r5=40, r6=1000, r7=1000 O r5=50, r6=1000, r7=996
- Please complete the binary encoding for the following BL instruction at address Ox2000 using the given information. Please write the answer in a group of four bits as follows: 0010 0010 0010 1100. Address Instructions 0x2000 bl sub 0x2004 add r3, r2, r1 0x2008 sub r6, r5, r3 sub: stmfd r13!, {r0-r12, 0X200C r14] 0x2010 add r7, r2, r5 Ox2014 mov r3, r2Evaluate the effect of the instruction LDR r1, [r2], #4, given the initial values below. What is the final values of (and pointed by) all the registers? What is the addressing mode of the given instruction? Registers: r1 = 30 r2 = 1004 r3 = 50 Memory Address Value 1000 15 1004 20 1008 5 1012 13 O r1=20,r2=1004, r3=50, pre-indexing auto-indexing mode O r1=20, r2=20, r3=20, pre-indexing mode O r1=20, r2=1004, r3=30, post auto-indexing mode O r1=20, r2=1008, r3=50, auto-indexing post indexing mode4 Question 1: Encoding branches & immediates We want to design a new K-format instruction for a branch-equal-immediate. A: What information would need to be encoded in a beq R2, 7, loop instruction? B: Why can't we have a beq R2, 7, loop instruction? and C: How could we fix this? Hint: think about the instruction encodings and what we need to encode such an instruction. Name Bit Fields A: beq R2, 7, loop needs to encode: 5 bits 6 bits 5 bits S bits 5 bits 6 bits R-Format op rs rt rd shmt funct I-format op rs rt address/immediate (16) J-format op target address (26) B: Why can't we have this with the R/I/J formats? K-format C: What tradeoff could we make to implement a K-format?
- The "Add immediate unsigned" MIPS instruction: addi Rt, Rs, Imm requires the immediate field to be extended from 16 bits to 32 bits. If the value of the immediate field is: 1111000011110000 what will be the sign extended value of this field from 16 bits to 32 bits? Choose the best answer. 01111111111111111111000011110000 O 11111111111111111111000011110000 O This is a trick question. You cannot sign extend a negative number O 00000000000000001111000011110000 10000000000000001111000011110000 This is a trick question. You cannot sign extend a positive numberIdentify the addressing modes & the value of the register Ro for each of given instructions if initial values of Ro= 1500, R1=3000, PC = 4000. ADDRESS VALUE 1000 1260 2000 1570 2900 1400 3000 1650 4000 1750 4102 1150 4500 1760 5000 1850 i) Ld Ro. #125 11) Ld. Ro. [3000] i11) Ld Ro. [Ri] iv) Ld Ro. -100[Ri] v) Ld Ro. [PC+100]We want to design a new K-format instruction for a branch-equal-immediate. A: What information would need to be encoded in a beq R2, 7, loop instruction? B: Why can't we have a beq R2, 7, loop instruction? and C: How could we fix this? Hint: think about the instruction encodings and what we need to encode such an instruction. A: beq R2, 7, loop needs to encode: B: Why can't we have this with the R/I/J formats? Name R-Format I-format J-format K-format C: What tradeoff could we make to implement a K-format? Bit Fields 6 bits op op op 5 bits rs rs 5 bits rt rt 5 bits 5 bits rd shmt funct address/immediate (16) 6 bits target address (26)