Design the MEMORY and I/O Subsystem based on the given specification with complete solutions. A microcomputer system with a 16-bit address bus and an 8-bit data bus uses memory-mapped I/O. It has 8KB of ROM starting at address 1000H constructed using 2048x8 chips; 8KB of RAM ending at address 4FFFH constructed using 4096x4 chips; a bidirectional I/O device at address E000H with control signal R'/W. a) Draw the memory map of the Memory and I/O subsystem also indicating on how many chips have been used for the design. b) Draw the ROM design that has the following control signals: ACTIVE HIGH CHIP ENABLE, ACTIVE LOW OUTPUT DISABLE. c) Draw the RAM design that has the following control signals: ACTIVE HIGH CHIP ENABLE, ACTIVE LOW OUTPUT DISABLE, ACTIVE HIGH WRITE ENABLE

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Design the MEMORY and I/O Subsystem based on the given specification with complete solutions.
A microcomputer system with a 16-bit address bus and an 8-bit data bus uses memory-mapped I/O. It
has 8KB of ROM starting at address 1000H constructed using 2048x8 chips; 8KB of RAM ending at
address 4FFFH constructed using 4096x4 chips; a bidirectional I/O device at address E000H with control
signal R'/W.
a) Draw the memory map of the Memory and I/O subsystem also indicating on how many chips have
been used for the design.
b) Draw the ROM design that has the following control signals: ACTIVE HIGH CHIP ENABLE, ACTIVE
LOW OUTPUT DISABLE.
c) Draw the RAM design that has the following control signals: ACTIVE HIGH CHIP ENABLE, ACTIVE
LOW OUTPUT DISABLE, ACTIVE HIGH WRITE ENABLE
d) Draw the I/O subsystem design that has the following control signals: ACTIVE HIGH ENABLE for
INPUT, ACTIVE HIGH LOAD for OUTPUT.
Transcribed Image Text:Design the MEMORY and I/O Subsystem based on the given specification with complete solutions. A microcomputer system with a 16-bit address bus and an 8-bit data bus uses memory-mapped I/O. It has 8KB of ROM starting at address 1000H constructed using 2048x8 chips; 8KB of RAM ending at address 4FFFH constructed using 4096x4 chips; a bidirectional I/O device at address E000H with control signal R'/W. a) Draw the memory map of the Memory and I/O subsystem also indicating on how many chips have been used for the design. b) Draw the ROM design that has the following control signals: ACTIVE HIGH CHIP ENABLE, ACTIVE LOW OUTPUT DISABLE. c) Draw the RAM design that has the following control signals: ACTIVE HIGH CHIP ENABLE, ACTIVE LOW OUTPUT DISABLE, ACTIVE HIGH WRITE ENABLE d) Draw the I/O subsystem design that has the following control signals: ACTIVE HIGH ENABLE for INPUT, ACTIVE HIGH LOAD for OUTPUT.
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